VLSI-CAD and Testing Reading Group  
  We are a group of Computer Enginerring faculty and students who meet to discuss research papers related to VLSI CAD and Testing areas. Everyone is welcome to join our meetings. If you like to join the mailing list, please email Azadeh Davoodi.  
  Fall 2011, Summer 2011, Spring 2011, Fall 2010, Spring 2010, Fall 2009, Summer 2009, Spring 2009Fall 2008, Summer 2008Spring 2008, Fall 2007.  

  Fall 2011: meetings TBA at 4610EH  
  Paper Title Presenter
09/23 Parallel Routing paper @ 3609 Zi

  Summer 2011: meetings TBA at 4610EH  
  Participants: Ammar Al Marzouqi, Hamid Shojaei, Min Li, Ye Hu, Azadeh Davoodi, Kewal Saluja.  
  Paper Title Presenter
08/26 Dangling-wire Avoidance Routing for Crossbar Switch Structured ASIC Design Style, IEEE-DAT 2010 Ye
08/15 Deflecting crosstalk by routing reconsideration through refined signal correlation estimation, GLSVLSI 2009 Ye
08/08 Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics, ICCAD 2005 Ammar
08/01 Routability-Driven Placement Ye
07/27 Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style, TCAD, December 2010 Ammar
07/08 NoC Slides Ammar
06/22 NoC Slides Ammar
06/17 Routing Architecture Exploration for Regular Fabrics, DAC 2004 Ammar

  Spring 2011: meetings Friday 3:30-5:00PM at 4610EH  
  Participants: Ahmed Fikri, Chunhua Yao, Hamid Shojaei, Min Li, Warin Sootkaneung, Ye Hu, Zachary Marzec, Azadeh Davoodi, Kewal Saluja.  
  Paper Title Presenter
02/25 Trusted design in FPGAs, DAC 2007 Ahmed
02/11 Ending Piracy of Integrated Circuits, IEEE Computers, 43(10):30-38, 2010. Ahmed
01/27 Routability-driven placement Azadeh

  Fall 2010: meetings Friday 3:30-5:00PM at 4610EH  
  Participants: Chunhua Yao, Deepika Ganju, Hamid Shojaei, Jung-Tai Tsai, Zachary Marzec, Min Li, Warin Sootkaneung, Zhilong Cong, Azadeh Davoodi, Kewal Saluja.  
  Paper Title Presenter
12/17 CANCELED A Reconfigurable Design-for-Debug Infrastructure for SoCs, DAC 2006 (remaining modes) Jung-Tai
12/03 A Reconfigurable Design-for-Debug Infrastructure for SoCs, DAC 2006 (signal capture mode) Jung-Tai
11/12  paper TBD (no meeting on 11/05) Jung-Tai
10/30 finish last week Warin
10/23 Design and Implementation of the AEGIS Single-Chip Secure Processor using Physical Random Functions, ISCA 2005 Jung-Tai
10/08 Design Methods for Security and Trust, DATE 2007 Min
09/24 finish last week Yao
09/17 A Survey of Hardware Trojan Taxonomy and Detection, IEEE Design & Test of Computers, 10(25), 2010 Azadeh

  Spring 2010: meetings Friday 3:30-5:00PM at 4610EH  
  Participants: Chen-Han Ho, Chunhua Yao, Hamid Shojaei, Lin Xie, Meng Shi, Min Li, Shreyas Parnerkar, Tai-Hsuan Wu, Warin Sootkaneung, Varun Vats, Azadeh Davoodi, Kewal Saluja.  
  Paper Title Presenter
03/05 Open House 
02/19 Explaining Cache SER Anomaly Using DUE AVF Measurement, HPCA 2010 Yao
02/05 A Microarchitecture-based Framework for Pre- and Post-Silicon Power Delivery Analysis, Micro 2009 Chen-Han
01/29 DynaTune: Circuit-level Optimization for Timing Speculation Considering Dynamic Path Behavior, ICCAD 2009 Azadeh

  Fall 2009: meetings Friday 3:30-5:00PM at 4610EH  
  Participants:Chunhua Yao, Hamid Shojaei, Lin Xie, Meng Shi, Shreyas Parnerkar, Tai-Hsuan Wu, Warin Sootkaneung, Azadeh Davoodi, Kewal Saluja.  
  Paper Title Presenter
10/23 Pentium Pro Processor Design for Test and Debug, ITC 1997 Hamid
10/16 Fast and Accurate Timing Characterization using Functional Information, IEEE TCAD 2001 Shreyas
10/09 Debug-related papers: p1, p2, p3. Hamid
09/18 False Timing Path Identification Using ATPG Techniques and Delay-Based Information, DAC 2002 Shreyas
09/11 VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects, IEEE TSM 2008 Meng
09/04 Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors, ISCA 2008 Yao

  Summer 2009: meetings Friday 3:30-5:00PM at 4610EH  
  Participants: Lin Xie, Chunhua Yao, Meng Shi, Hamid Shojaei, Michael Anderson, Warin Sootkaneung, Azadeh Davoodi, Kewal Saluja.  
  Paper Title Presenter
08/14 Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation, MICRO 2007 Hamid
08/07 IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localizatio, DAC 2008 Michael

  Spring 2009: meetings Friday 4:00-5:00PM at 4610EH  
  Participants: Lin Xie, Tai-Hsuan Wu, Chunhua Yao, Meng Shi, Dongkeun Oh, Hamid Shojaei, Michael Anderson, Shreyas Parnerkar, Azadeh Davoodi, Kewal Saluja.  
  Paper Title Presenter
04/17 Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models, DATE 2007 Shreyas
04/10 On process variation tolerant low cost thermal sensor design in 32nm CMOS technology, GLSVLSI 2009 Yao
04/03 Removing user-specified false paths from timing graphs, DAC 2000 Shreyas
03/27 Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors, ICCAD 2008 Thomas
03/13 A framework for predictive dynamic temperature management of microprocessor systems, ICCAD 2008 Yao
03/06 Open House--no meeting  
02/27 Thermal-Aware Floorplanning Tai-Hsuan
02/13 BDD and Pareto Calculator, CODES+ISSS 2008 Hamid
02/06 3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method, ISQED 2007 Thomas
01/23 Thermal-Aware Floorplanning for Task Migration Enabled Active Sub-threshold Leakage Reduction, ICCAD 2008 Yao

  Fall 2008: meetings Friday 4:00-5:00PM at 4610EH  
  Participants: Lin Xie, Tai-Hsuan Wu, Chunhua Yao, Meng Shi, Azadeh Davoodi, Kewal Saluja.  
  Paper Title Presenter
12/02 Statistical foundations of data analysis and modeling (from DFM book) Meng
11/07 Overview of variability: sources, test structures, modeling (from the DFM book) Meng
10/24 Visitors from Japan  
10/10 Thermal-Aware Floorplanning Yao
10/03 Power-Aware Placement, DAC 2005 Tai-Hsuan
09/26 Continue of 09/19 all
09/19 An Efficient Pruning Method to Guide the Search of Precision Tests in Statistical Timing Space, ITC 2006 all

  Summer 2008: meetings Friday 12:00-1:30PM at 4610EH  
  Participants: Lin Xie, Tai-Hsuan Wu, Chunhua Yao, Meng Shi, Iwao Yamazaki, Azadeh Davoodi, Kewal Saluja.  
  Paper Title Presenter
08/15 Global Routing Overview Tai-Hsuan
08/01 A Tutorial on Built-In Self-Test Yao
07/25 Silicon Speedpath Measurement and Feedback into EDA Flow, DAC 2008 all
07/18 Optimal Margin Computation for At-Speed Test, DATE 2008 Lin

  Spring 2008: meetings Friday 3:30-5:00PM at 4610EH  
  Participants: Anuj Kumar, Warin Sootkaneung, Lin Xie, Iwao Yamazaki, Chunhua Yao, Tai-Hsuan Wu, Michael Anderson, Brian Hickman, Chuck Tsen, Azadeh Davoodi, Kewal Saluja.  
  Paper Title Presenter
05/16 Mini Tutorial on TCL Scripting in Cadence Anuj
05/09 Anuj goodbye, Jade Garden@noon  
05/02 Mini Tutotial on Master-Worker Framework APIs for Optimization in Condor Tai-Hsuan
04/25 Grid-Based Optimization for High Performance Design Using Condor Tai-Hsuan
04/18 Paper on Power-Aware Buffer Insertion Anuj
04/11 Paper on Gate Sizing Tai-Hsuan
04/04 Word Oriented Random-Access-Can Based BIST Yao
03/14 Adapting to Intermittent Faults in Multicore Systems Warin
03/07 A Parallel Dynamic Programming Algorithm on A Multi-Core Architecture Tai-Hsuan
02/29 Prof. Memik Visiting  
02/22 Prof. Mitra Visiting  
02/15 The Impact of Multi-Core on Computational Science Software Tai-Hsuan
02/08 Physically-Aware Test Development  
02/01 Physical Synthesis with Incremental Placement and Exact Timing Estimation Anuj

  Fall 2007: meetings Friday 3:30-5:00PM at 4610EH  
  Participants: Anuj Kumar, Warin Sootkaneung, Lin Xie, Iwao Yamazaki, Chunhua Yao, Tai-Hsuan Wu, Eric Hill, Sanghamitra Roy, Azadeh Davoodi, Kewal Saluja.  
  Paper Title Presenter
12/07 An Efficient Perspective for Variability Characterization of Complex VLSI Circuits Lin
11/30 Enhancing Design Robustness with Reliability-Aware Resynthesis and Logic Simulation, ICCAD 2007 Tai-Hsuan
11/02 Soft Error Reduction in Combinational Logic Using Gate Resizing and Flipflop Selection, ICCAD 2006 Tai-Hsuan
10/26 Trading Off Transient Fault Tolerance and Power Consumption in Deep Submicron VLSI Circuits, TVLSI 2004 Yao
10/19 Fault Sensitivity Analysis and Reliability Enhancement of Analog-to-Digital Converters, TVLSI 2003 Warin
10/12 FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Design, ISQED 2006 all
09/28 Razor: Circuit-level Correction of Timing Errors for Low-Power Operation, MICRO 2004 Warin
09/14 Assessing SEU Vulnerability via Circuit-Level Timing Analysis, WAR-1 Tai-Hsuan
09/07 Automating Post-Silicon Debugging and Repair, ICCAD 2007 Anuj
08/31 Confidence Scalable Post-Silicon Statistical Delay Prediction Under Process Variations, DAC 2007 Lin
08/24 Demonstration of A Modern Physical Design Flow Using Cadence Anuj