Current projects:
Past projects:
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Bridging the gap between global and detailed routing of IC
(Supported by NSF-CCF, tool support by Mentor Graphics, TraPL, GR2DR)
As semiconductor technology enters the sub-10nm era, it has significantly complicated the computer-aided design of ICs. Today's designer must deal with increasingly complex rules, imposed by the manufacturing facility so as to ensure that the chip can be successfully fabricated. This project aims to develop CAD tools that incorporate major design rules within a key, higher stage of the design flow, namely the global routing stage. By integrating these rules into global routing, the project aims to accelerate the progress of IC design within the sub-10nm regime.
Related Publications:
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D. Shi, and A. Davoodi, "TraPL: Track Planning of Local congestion for global routing", IEEE/ACM Design Automation Conf. (DAC'17), Article No.19, 6 pages, June 2017.
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D. Shi, E. Tashjian, and A. Davoodi,
"Dynamic planning of local congestion from varying-size vias for global routing layer assignment",
IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD'17), Vol. 36, No. 8, pp. 1301-1312, August 2017.
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D. Shi, and A. Davoodi, "Improving detailed routability and pin access with 3D monolithic standard cells", ACM Int'l Symp. on Physical Design (ISPD'17), pp. 107-112, March 2017.
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D. Shi, E. Tashjian, and A. Davoodi,
"Dynamic planning of local congestion from varying-size vias for global routing layer assignment",
Asia South-Pacific Design Automation Conf. (ASPDAC'16), pp. 372-377, January 2016.
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Hardware security
(Supported by WARF)(Word-RevEng, SplitMan)
The goal of this project is to study and enhance the security of IC design and manufacturing. This includes security of IC manufacturing using an untrusted third party and design techniques to protect the Intellectual Property (IP) inside the IC.
Related Publications:
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B. Zhang, J. Magana, and A. Davoodi,
"Analysis of security of split manufacturing using machine learning", to appear in Design Automation Conf. (DAC'18), June 2018.
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A. Davoodi, "Golden-Free Trojan Detection", invited book chapter in The Hardware Trojan War: Attacks, Myths, and Defenses, pp. 203-215, ISBN 978-3-319-68511-3, Springer 2018.
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J. Magana, D. Shi, J. Melchert, and A. Davoodi,
"Are proximity attacks a threat to the security of split manufacturing of Integrated Circuits?",
IEEE Trans. on VLSI (TVLSI'17), Vol 25, No. 12, pp. 3406-3419, December 2017.
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J. Magana, D. Shi, and A. Davoodi,
"Are proximity attacks a threat to the security of split manufacturing of Integrated Circuits?",
Int'l Conf. on Computer-Aided Design (ICCAD'16), 7 pages, November 2016.
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E. Tashjian, and A. Davoodi,
"On using control signals for word-level identification in a gate-level netlist", Design Automation Conf. (DAC'15), June 2015.
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M. Li, A. Davoodi, and M. Tehranipoor, "
A sensor-assisted self-authentication framework for hardware
Trojan detection", IEEE Design & Test of Computers (D&TC'13), Vol. 30, No. 5, pp. 74-82, October 2013;
also Design, Automation, and Test in Europe (DATE'12), pp. 1331-1336, March 2012.
(Slides)
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H. Shojaei, A. Davoodi, and P. Ramanathan, "Confidentiality
preserving integer programming for global routing",
Design Automation Conf. (DAC'12), pp. 709-716, June 2012. (Slides)
The complexity of modern day electronic systems combined with nano-scale non-idealities have made
"post-silicon" validation significantly cumbersome.
At this stage few fabricated chips are verified for correct functionality under different workload and operating conditions in order to detect and fix
the bugs which have escaped the design stage. The process has become time-consuming and expensive due to the costs of equipments and of increasing silicon re-spins,
the use of manual techniques, and the complicated nature of bugs in nano-scale technologies. Consequently, time-to-market and profit are directly at stake.
The major challenge at the post-silicon stage is lack of observability and limitation to an interface of at most a few thousand pins to reason about billions of
nano-scale components. A bug needs to be detected, localized in time and space, ideally at path-level resolution, within a time window of few clock cycles.
It may not always be possible to regenerate a detected bug because the bugs may be inter-dependent. In addition, the root-cause of a bug, such as static manufacturing
variations or transient ground and power supply fluctuations, need to be identified for more effective detection and analysis of the bugs.
The most challenging type of bug at the post-silicon stage can perhaps
be considered to be timing errors. Timing errors refer to those malfunctions which manifest in the form of
setup and hold time violations on logic. Although small in number, timing errors can take the majority of the post-silicon validation cycle. Identifying timing errors is crucial to
the majority of the
domains of the electronic industry including microprocessors, System on Chips integrating Intellectual Properties, and ASICs, in which meeting a target frequency is a necessity.
The objective of this research is to bring automation to the debug process of timing errors. Our vision is to rely on few on-chip measurements to bring valuable information about the internal
timing characteristics of the chip. Our goal, on one hand, is identification of on-chip measurement sites (as existing circuit components), and design of new structures
(to be embedded on-chip) which enhance the "timing observability". On the other hand, at the post-silicon stage, we aim to develop analysis methods to reason about the chip’s internal timing
behavior by utilizing the measurements.
Related Publications:
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M. Li, and A. Davoodi, "Multi-mode trace signal selection for post-silicon debug",
Asia and South Pacific Design Automation Conf. (ASPDAC'14), pp. 640-645, January 2014.
(Slides)
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M. Li, and A. Davoodi, "A hybrid approach for fast and
accurate trace signal selection for post-silicon debug", IEEE Trans. on CAD (TCAD'14), Vol. 33, No. 7, pp. 1081 - 1094, June 2014;
also in Design, Automation, and Test in Europe (DATE'13),
pp. 485-490, March 2013; and in Int'l Workshop on
Microprocessor Test and Verification (MTV'12), December
2012. (Slides)
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M. Li, A. Davoodi, and L. Xie, "Custom
on-chip sensors for post-silicon failing path isolation in the
presence of process variations", Design, Automation, and Test in Europe (DATE'12),
March 2012.
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L. Xie, and A. Davoodi, "Post-silicon failing path isolation
incorporating the effects of process variations", IEEE Trans. on CAD of Integrated Circuits and Systems
(TCAD),
Vol. 31, No. 7, pp. 1008-1018, July 2012;
also paper in
Design Autom. Conf. (DAC'10),
pp. 386-391, June 2010.
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H. Shojaei, and A. Davoodi, "Trace
selection for improving timing and logic visibility in post-silicon
validation",
Int'l Conf. on Computer-Aided Design (ICCAD'10),
pp. 168-172, November 2010.
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L. Xie, A. Davoodi, and K. K. Saluja,
"Post-silicon diagnosis of segments on failing speedpaths due to manufacturing variations",
Design Autom. Conf. (DAC'10),
pp. 274-279, June 2010.
The high volume and complexity of cells and interconnect structures in modern designs are causing serious challenges to routability. Rapid congestion analysis (which may be defined as quick identification of the congestion spots on the layout) can help the routability problem relatively early, for example during placement and in conjunction with global routing. Increasing the correlation between global routing and detailed routing is another major challenge to routability.
In modern designs, several new factors contribute to routing congestion including significantly different wire size and spacing among the metal layers, sizes of inter-layer vias, various forms of routing blockages (e.g., reserved for power-grid, clock network, or IP blocks in an SoC), local congestion due to pin density and wiring inside a global-cell, and virtual pins located at the higher metal layers. In view of the above, the objective of this research is to develop techniques for congestion analysis at the global routing stage, for rapid analysis, and for increasing the correlation with detailed routing.
Related Publications:
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D. Shi, A. Davoodi, and J. T. Linderoth
"A procedure for improving the distribution of congestion in global routing",
Design, Automation, and Test in Europe (DATE'16), pp. 249-252, March 2016.
H. Shojaei, A. Davoodi, and J. Linderoth,
"Planning for local net congestion in global routing",
Int'l Symp. on Physical Design (ISPD'13), pp. 85-92, March 2013. [Slides]
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H. Shojaei, A. Davoodi, and J. Linderoth, "Congestion
analysis for global routing via integer programming", Int'l
Conf. on Computer-Aided Design (ICCAD'11), pp.
256-262, November 2011. (Slides)
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H. Shojaei, A. Davoodi, and T. Basten, "Collaborative
multi-objective global routing", IEEE Trans. on VLSI (TVLSI), Vol. 21, No. 7, pp. 1308-1321, July 2013; also a related
paper in Int'l Symp. on Low Power Electronics and Design
(ISLPED'10), pp. 407-412, August 2010.
Design of today's electronic systems would not be possible without the tools that automate the process of integrating billions of nano-scale components--e.g.
into the "brain" of an iPhone. As technology advances towards mobile devices that are smaller yet more powerful, these tools need to evolve as fast as the
systems that they help design--in fact faster, because the nano-scale components not only grow in numbers but also shrink in size, bringing along with them new
challenges.
To improve existing design-aid tools, a new window of
opportunity has arisen due to the emergence of a more powerful
yet affordable and secure computational platform: a cloud of
multi-core computers working together as if it were one enormous
machine. By leveraging this cloud computing platform the proposed research investigates
alternative design automation strategies which traditionally were deemed to be too time-consuming.
One focus of the research is to improve an important step of the design process
known as global routing, the step in which designers plan how the billions of nano-scale components will be interconnected on the chip. This planning can
significantly impact the severity of many issues in subsequent stages of the
design cycle, yet it has to be done quickly. With the aid of large-scale parallelism provided by computational grids, the research aims to demonstrate
that the use of a computational technique called integer programming, which was
previously viewed as too time-consuming for global routing, can help generate
significantly higher quality solutions while meeting practical runtime requirements.
Related Publications:
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T.-H. Wu, A. Davoodi, and J. Linderoth "Power-driven global routing for MSV domains",
Design, Automation, and Test in Europe (DATE'11),
pp. 443-448, March 2011.
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T.-H. Wu, A. Davoodi, and J. Linderoth, "GRIP: Global Routing via Integer Programming",
IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD'11),
Vol. 30, No. 1, pp. 72-84, January 2011;
also in
Design Autom. Conf. (DAC'09),
pp. 320-325, July 2009.
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T.-H. Wu, A. Davoodi, and J. Linderoth,
"A parallel integer programming approach to global routing",
Design Autom. Conf. (DAC'10),
pp. 194-199, June 2010. (Best Paper Candidate)
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T.-H. Wu, and A. Davoodi, "PaRS: parallel and near-optimal grid-based cell sizing for library-based design",
IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD'09),
Vol. 28, No. 11, 1666-1678, November 2009;
also in
Int'l Conf. on Computer-Aided Design (ICCAD'08),
pp. 107-111, November 2008.
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T.-H. Wu, L. Xie, and A. Davoodi,
"A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing",
Journal of Low Power Electronics,
Vol. 4, No. 2, pp. 191-201, August 2008 [.PDF];
also in
Int'l Symp. on Low Power Electronics and Design (ISLPED’08),
pp. 45-50, August 2008.
In today's technology, a single IC (e.g., the part of an iPhone that serves as the "brain") integrates billions of nano-scale components.
These components are packed in a tiny space, yet provide amazingly diverse functionalities (multimedia, internet, phone) with high-speed, while consuming very low power.
As the components continue to shrink in size, however, current technology faces steeper challenges in delivering the products of the next generation.
A major challenge stems from the imperfections in IC fabrication: smaller components are less tolerant to these imperfections; their performance may turn out so poor that
the IC may have to be entirely redesigned in order to meet the performance specs. This means delayed delivery of the final product, which means major loss of market opportunities.
This research aims to develop a mathematical framework for producing IC designs that are robust with respect to fabrication imperfections.
A highlighting feature of this framework is that it requires only a limited knowledge of the manufacturing process--e.g., rather than relying on detailed information on manufacturing inaccuracies,
it suffices in this framework to know only some bounds on the degree of imperfections. This is important since the designers often don't have access to detailed data on these inaccuracies --
they may not exist, or, third-party manufacturers may not release them. So
the goal is to have a framework which is not only robust with respect to manufacturing errors, but also less dependent on the knowledge of them.
Related Publications:
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L. Xie, and A. Davoodi, "Bound-based
statistically-critical path extraction under process variations",
IEEE Trans. on CAD of
Integrated Circuits and Systems (TCAD'11),
Vol. 30, No. 1, pp. 59-71, January 2011;
also in
Asia and South Pacific Design Autom. Conf. (ASPDAC'09),
pp. 278-283, January 2009.
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L. Xie, A. Davoodi, J. Zhang, and T.-H. Wu, "Adjustment-based modeling for timing analysis under variability",
IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD'09),
Vol. 28, No. 7, pp. 1085-1095, July 2009;
also in
Int'l Conf. on Computer-Aided Design (ICCAD'08),
pp. 181-184, November 2008.
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L. Xie, and A. Davoodi,
"Robust estimation of timing yield with partial statistical information on process variations",
IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD'08),
Vol. 27, No. 12, pp. 2264-2276, December 2008;
also in
Int'l Symp. on Quality Electronic Design (ISQED'08),
pp. 156-161, March 2008.
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L. Xie, A. Davoodi, K. K. Saluja, and A. Sinkar,
"False path aware timing yield estimation under variability",
IEEE VLSI Test Symp. (VTS'09),
pp. 161-166, May 2009.
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