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WISCAD
VLSI Design Automation Lab
University of Wisconsin Madison
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Journal | Conference | Workshop | Patent | Other

Journal

  • L. Xie, and A. Davoodi, "Bound-based identification of timing-violating paths under variability", submitted to IEEE Transactions on CAD of Integrated Circuits and Systems (TCAD).

  1. T.-H. Wu, and A. Davoodi, "PaRS: parallel and near-optimal grid-based cell sizing for library-based design", accepted for publication in IEEE Transactions on CAD of Integrated Circuits and Systems (TCAD'09).

  2. L. Xie, A. Davoodi, J. Zhang, and T.-H. Wu, "Adjustment-based modeling for timing analysis under variability", IEEE Transactions on CAD of Integrated Circuits and Systems (TCAD'09), Vol. 28, No. 7, pp. 1085-1095, July 2009.

  3. L. Xie, and A. Davoodi, "Robust estimation of timing yield with partial statistical information on process variations", IEEE Transactions on CAD of Integrated Circuits and Systems (TCAD'08), Vol. 27, No. 12, pp. 2264-2276, December 2008.

  4. T.-H. Wu, L. Xie, and A. Davoodi, “A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing”, Journal of Low Power Electronics, Vol. 4, No. 2, pp. 191-201, August 2008. [.PDF]

  5. A. Davoodi, and A. Srivastava, "Variability-driven gate sizing for binning yield optimization", IEEE Transactions on VLSI (TVLSI’08), Vol. 16, No. 6, pp. 683-692, June 2008.

  6. L. Xie, and A. Davoodi, "Fast and accurate statistical static timing analysis with skewed process parameter variation", IET Circuits, Devices & Systems, Vol 2, No. 2, pp. 187-200, April 2008.

  7.  A. Davoodi, V. Khandelwal, and A. Srivastava, "Probabilistic evaluation of solutions in variability-driven optimization", IEEE Transactions on CAD of Integrated Circuits and Systems (TCAD'06), Vol. 25, No. 12, pp. 3010-3016, December 2006.

  8. L. Wang, M. French, A. Davoodi, and D. Agarwal, "FPGA dynamic power minimization through placement and routing constraints", EURASIP Journal on Embedded Systems, Special Issue on Field Programmable Gate Arrays (EURASIP JES'06), 4th Quarter, 2006.

  9. J. L. Wong, A. Davoodi, V. Khandelwal, A. Srivastava, and M. Potkonjak, "A statistical methodology for wire-length prediction", IEEE Transactions on CAD of Integrated Circuits and Systems (TCAD'06), Vol. 25, No. 7, pp. 1327-1336, July 2006.

  10.  A. Davoodi, and A. Srivastava, "Effective techniques for the generalized low power binding problem", ACM Transactions on Design Automation of Electronic Systems, (TODAES'06), Vol. 11, No. 1, pp. 52-69, January 2006.

  11. A. Davoodi, and A. Srivastava, "Power-driven simultaneous resource binding and floorplanning: a probabilistic approach", IEEE Transactions on VLSI Systems (TVLSI'05), Vol. 13, No. 8, pp. 934-942, August 2005.

  12. V. Khandelwal, A. Davoodi, and A. Srivastava, "Simultaneous Vt selection and assignment for leakage optimization", IEEE Transactions on VLSI Systems (TVLSI'05), Vol. 13, No. 6, pp. 762-765, June 2005.

  13. A. Davoodi, and A. Srivastava, "Voltage scheduling under unpredictabilities: A risk management paradigm", ACM Transactions on Design Automation of Electronic Systems (TODAES'05), Vol. 10, No. 2, pp.354-368, April 2005.

  14. A. Davoodi, V. Khandelwal, and A. Srivastava, "Empirical models for net-length probability distribution and applications", IEEE Transactions on VLSI Systems (TVLSI'04), Vol. 12, No. 10, pp. 1066-1075, October 2004.

Conference

  1. M. J. Anderson, A. Davoodi, J. Lee, A. Sinkar, and N. S. Kim, "Statistical timing analysis considering leakage variability in power-gated designs", ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'09), pp. 57-62, August 2009.

  2. T.-H. Wu, A. Davoodi, and J. T. Linderoth, "GRIP: scalable 3-D global routing using integer programming", IEEE Design Automation Conference (DAC'09), pp. 320-325, July 2009. [read this note about GRIP solutions]

  3. L. Xie, A. Davoodi, K. K. Saluja, and A. Sinkar, "False path aware timing yield estimation under variability", IEEE VLSI Test Symposium (VTS'09), pp. 161-166, May 2009.

  4. L. Xie, and A. Davoodi, "Bound-based identification of timing-violating paths under variability", ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC'09), pp. 278-283, January 2009.

  5. L. Xie, A. Davoodi, J. Zhang, and T.-H. Wu, "Adjustment-based modeling for statistical static timing analysis with high dimension of variability", ACM/IEEE International Conference on Computer-Aided Design (ICCAD'08), pp. 181-184, November 2008.

  6. T.-H. Wu, and A. Davoodi, "PaRS: Fast and near-optimal grid-based cell sizing for library-based design", ACM/IEEE International Conference on Computer-Aided Design (ICCAD'08), 107-111, November 2008.  [.PDF extended version under revision]

  7. A. Kumar, T.-H. Wu, and A. Davoodi, "SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement", pp. 551-556, ACM/IEEE International Conference on Computer Design (ICCD'08), October 2008.

  8. T.-H. Wu, L. Xie, and A. Davoodi, “A parallel and randomized algorithm for large-scale dual-Vt assignment and continuous gate sizing”, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’08), pp. 45-50, August 2008. [.PDF of extended journal version]

  9. J. Lee, L. Xie, and A. Davoodi, "A dual-Vt low leakage SRAM array robust to process variations", ACM/IEEE International Symposium on Circuits and Systems (ISCAS'08), pp. 580-583, May 2008.

  10. L. Xie, and A. Davoodi, "Robust estimation of timing yield with partial statistical information on process variations", ACM/IEEE International Symposium on Quality Electronic Design (ISQED'08), pp. 156-161, March 2008.

  11. L. Xie, and A. Davoodi, "Fast and accurate statistical static timing analysis with skewed process parameter variation", ACM/IEEE International Symposium on Quality Electronic Design (ISQED'08), pp.712-717, March 2008.

  12. J. Wong, A. Davoodi, V. Khandelwal, A. Srivastava, and M. Potkonjak, "Statistical timing analysis using kernel smoothing", ACM/IEEE International Conference on Computer Design (ICCD'07), pp. 97-102, October 2007.

  13. J. Lee, and A. Davoodi, "Comparison of dual-Vt configurations of SRAM cell considering process-induced Vt variations", ACM/IEEE International Symposium on Circuits and Systems (ISCAS'07), pp. 3018-3021, May 2007.

  14. A. Dobhal, V. Khandelwal, A. Davoodi, and A. Srivastava, "Variability driven joint leakage-delay optimization through gate sizing with provabale convergence", International Conference on VLSI Design (VLSID'07), pp. 571-576, January 2007.

  15. A. Davoodi, and A. Srivastava, "Variability-driven gate sizing for binning yield optimization", ACM/IEEE Design Automation Conference (DAC'06), pp. 959-964, July 2006.

  16. A. Davoodi, and A. Srivastava, "Probabilistic evaluation of solutions in variability-driven optimization", ACM International Symposium on Physical Design (ISPD'06), pp. 17-24, April 2006 (featured EETimes 04/07/06).

  17. A. Davoodi, and A. Srivastava, "Variability-driven buffer insertion considering correlations", ACM/IEEE  nternational Conference on Computer Design (ICCD'05), pp. 425-430, October 2005.

  18. A. Davoodi, and A. Srivastava, "Probabilistic dual-Vth leakage optimization under variability", ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'05), pp. 143-148, August 2005.

  19. A. Davoodi, and A. Srivastava, "Wake-up protocols for controlling current surges MTCMOS-based technology", ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC'05), pp. 868-871, January 2005.

  20. A. Davoodi, and A. Srivastava, "Simultaneous floorplanning and binding: A probabilistic approach", ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC'05), pp. 517-522, January 2005.

  21. A. Davoodi, V. Khandelwal, and A. Srivastava, "Variability inspired implementation selection problem", ACM/IEEE International Conference on Computer Aided Design (ICCAD'04), pp. 423-427, November 2004.

  22. J. Wong, A. Davoodi, V. Khandelwal, A. Srivastava, and M. Potkonjak, "Wire-length prediction using statistical techniques", ACM/IEEE International Conference on Computer Aided Design (ICCAD'04), pp. 702-705, November 2004.

  23. V. Khandelwal, A. Davoodi, and A. Srivastava, "Efficient statistical timing analysis through error budgeting", ACM/IEEE International Conference on Computer Aided Design (ICCAD'04), pp. 473-476, November 2004.

  24. A. Davoodi, V. Khandelwal, and A. Srivastava, "High level techniques for power-grid noise immunity", ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI'04), pp. 13-18, April 2004.

  25. V. Khandelwal, A. Davoodi, A. Nanavati, and A. Srivastava, "A probabilistic approach to buffer insertion", ACM/IEEE International Conference on Computer Aided Design (ICCAD'03), pp. 560-567, November 2003 (nominated for best paper award).

  26. A. Davoodi, and A. Srivastava, "Voltage scheduling under unpredictabilities: A risk management paradigm", ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'03), pp. 302-305, August 2003.

  27. A. Davoodi, and A. Srivastava, "Effective graph theoretic techniques for the generalized low power binding problem", ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'03), pp. 152-257, August 2003.

Workshop

  1. T.-H. Wu, L. Xie, and A. Davoodi, “A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing”, ACM/IEEE International Workshop on Logic and Synthesis (IWLS'08), June 2008.

  2. A. Kumar, and A. Davoodi, “SynECO: Technology remapping with incremental constrained placement and exact timing estimation”, ACM/IEEE International Workshop on Logic and Synthesis (IWLS'08), June 2008.

  3. A. Davoodi, and J. Lee, "A dual-Vt assignment algorithm of SRAM array considering process-induced Vt variations", ACM/IEEE International Workshop on Logic and Synthesis (IWLS'07), May-June 2007.

  4. A. Davoodi, and A. Srivastava, "Variability driven gate sizing for binning yield optimization", ACM/IEEE International Workshop on Logic and Synthesis (IWLS'06), June 2006.

  5. A. Davoodi, and A. Srivastava, "Variability driven buffer insertion considering correlations", ACM/IEEE International Workshop on Logic and Synthesis (IWLS'05), June 2005.

  6. A. Davoodi, and A. Srivastava, "Efficient stochastic pruning for variability-driven dual-Vth leakage optimization", ACM/IEEE International Workshop on Logic and Synthesis (IWLS'05), June 2005.

  7. A. Davoodi, and A. Srivastava, "Simultaneous floorplanning and binding: A probabilistic approach", ACM/IEEE International Workshop on Logic and Synthesis (IWLS'04), June 2004.

Patent

  1.  M. French, L. Wang, D. Agrawal, and A. Davoodi, "Low-power Intelligent Tool Environment (LITE) for FPGAs", patent application filed.

Other

  1. A. Kumar, and A. Davoodi, "Demonstration of a modern physical design flow using the silicon virtual prototyping back-end tools of Cadence", demo and poster presentation at the SIGDA University Booth at the Design Automation Conference, special session on Microelectronics Systems Education, 2007.

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