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Jake Adriaens
Fall 2005:
Experimental Evaluation of Low-Power Zigbee Wireless Sensor Networks (pdf)
This paper is a summary of my masters project under the guidance of Seapahn Megerian.
Recently wireless sensor networks have become a growing area of research and development due to the tremendous number of applications that can greatly benefit from such systems. To keep up with this trend, it is important to have experimental platforms for analysis and verification, that are cost effective, flexible, and easy to use. In this project, we investigate the experimental use and evaluation of a Zigbee-based wireless sensor network platform. We begin by presenting the details of the hardware and system software used (e.g. MAC and routing) and a number of applications to exercise the various components. The applications include accelerometer-based location tracking of a mobile node, video surveilance, and multimedia appliance control. We also present several experimentally observed power consumption data, where applicable.
Spring 2005:
HAXOR Home Automation and Observation Remote (pdf)
Abstract (pdf)
Collaborated with: Seapahn Megerian
Honorable mention in the Freescale wireless design challenge
Contest put on by: Freescale Semiconductor and Circuit Cellar Magazine
The HAXOR Home Automation and Observation Remote is a general purpose remote control infrastructure designed to integrate into advanced smart spaces such as next generation homes, offices, public venues, and other environments. The system is comprised of a number of wirelessly networked remote control, sensor, and actuator nodes, as well as multi-purpose base stations, and other backbone fabrics that seamlessly work together to provide a number of services to the end-users. The source code includes a framework for multi-hop routing using the Freescale 13192 802.15.4 compliant wireless boards, as well as a remote control for the popular mp3 player Winamp.
Source Code (zip)
A Software Layer for IDE Disk Fault Injection (pdf) (ps)
Collaborated with: Dan Gibson
Course: CS736 Advanced Operating Systems
Instructor: Remzi Arpaci-Dusseau
Increasing demands for reliability, fault isolation, and fault tolerance have emphasized the need to study systems under failure conditions. Commodity disk systems have been studied for many years with simple assumptions about how they fail. To provide enabling technology for new research in more reliable file systems, disk system, and I/O interfaces, we present a flexible, software-based fault injection system, targeted for commodity disks running in conjunction with a commodity operating system. We present five sophisticated but general failure models, and a simple interface to allow arbitrary faults to be injected rapidly and without permanent hardware damage. We also evaluate the performance of a common file system utility to detect these faults, and present a summary of our findings.
Source Code (tar.gz)
Collaborated with: Venkata Suman Sanikommu, Kamal Srinivasan, Sukanya Thiagarajan
Course: ECE752 Advanced Computer Architecture I
Instructor: Mikko Lipasti
Modern processors use two or more levels of cache hierarchy to alleviate the problem of mismatch in processor speeds and memory access latency. Increasing the cache size, associativity or even making the cache a fully associative one causes the access latency to go higher but, reduces the miss rates. These techniques reduce conflict misses yet their overall efficiency is adversely affected for applications where the demand varies on a per set basis. This problem can be resolved by introducing a variable way cache based on the application demand. The V-Way set associative cache design as proposed by M.K.Quereshi et. al reduces the second level cache miss rate by 13 % and this corresponds to an average IPC improvement of 8 %. This report is an attempt to validate and analyze the claims made by the authors of the V-Way cache design.
Note: It has been pointed out we may have incorrectly implemented the v-way cache. I have taken this paper down until I am able to correct any errors. My apologies to the authors of the v-way cache.
Fall 2004:
A Multithreaded Genetic Floorplanning Algorithm (pdf)
Course: ECE556 Design Automation of Digital Systems
Instructor: Yu Hen Hu
This paper presents my implementation of a multithreaded genetic floorplanning algorithm, including a short discussion of the motivation for producing a multithreaded floorplanner, some highlights of the algorithm and some empirical results.
Source Code (tar.gz)
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