General Guidelines
What is the general guideline for using Verilog?
Behavioral Verilog is only allowed for control logic. The rest of the design should be done in structural Verilog (and/or/not/nand/nor gates) or by using the schematic design.
Is there anything I can use to speed up my design process?
You can make use of the
MegaWizard Plug-In Manager to create some modules for you. This includes RAM, decoder,
adder, multiplier, etc. Here's how:
- Add a symbol by using right click
- Click on MegaWizard Plug-In Manager
- Create a new custom megafunction variation
- Under Gates -> LPM_DECODE/LPM_MUX...depending on which function you want to create.
- Customize the megafunction accordingly
Will the ALU be clocked? I think it will be, since we
were asked to use flip flops. Then is the addition/ subtraction
output be displayed at the NEXT state or in the current state?
The ALU alone is NOT clocked. The result of the
addition/substraction should be displayed within the same cycle
in the ALU. However, the entire datapath/processor design will
be clocked. As course progresses, you will learn more about the datapath design and pipeline techniques.
Can I design some modules in schematic and some in Verilog and stitch them together?
Yes you can.
- Use Verilog module in schematic - Create a symbol file for the Verilog module and you should be able to utilize that Verilog module using the insert symbol method.
- Use schematic module in Verilog - You can instantiate a
schematic module as you are instantiating a Verilog module. Just
remember to specify the port mapping. If you don't know how to do
it, perform File -> Create/Update -> Create Verilog Instantiation
Template Files for Current File to find out.
Installation and License Setup
What is the variable name and value to set up the license?
Please refer to the slide #11 in the discussion_01_quartus_ii.pdf
file. The variable name should be LM_LICENSE_FILE
and the value is specified in the "server info.txt" file. The form
of the value should be [port]@[server].
Project Setup
and Device Information
Which device should I choose when creating a new project?
Please choose Stratix EP1S80F1508C5.
You should have enough speed and space to fit in all your design
with this target device. You can change the target device from
Assignments -> Device
Where can I find out more about the FPGA we
are using?
Please refer to the handbook here (
link).
You can find out the
number of memory
blocks,
memory operations,
number of logic elements, etc.
This is a handbook for all Stratix family. When referring to
specific information for the device we chose, check out
EP1S80. You can also find out
about the memory operations here (
link).
How to implement a variable shifter - a shifter which
shifts variable amounts of bits?
Utilize Megafunction - lpm_clshift.
Memory
What is the format of the Memory Initialization File (.mif)?
Refer to this page (
link).
Memory initialized from the Megawizard incurs two
cycles delay. How to mitigate this problem?
Here are a few hints:
- You can actually reduce the delay to 1 cycle. In
Regs/Clken/Byte Enable/Aclrs page, you can deselect 'q' output port in the Which ports should be registered? groupbox. This will reduce the delay by one cycle.
- If you want to keep the register at the q output, think
about how to fuse the pipeline register with the supplied q output
register.
- If you are worried about old values being read from the memory
while reading and writing to the same address, you will probably
need to think about additional forwarding!
Simulation
I do not get the option of 'Multiple Items' in the insert node.
You will not be able to choose 'Multiple Items' from the drop
down menu. When you select multiple input/output pins from the node
finder, it will be automatically changed to 'Multiple Items'.
I am getting the following error.
Error: Specified license does not contain information required
to run the Quartus II software Error: Quartus II Full Compilation
was unsuccessful. 1 error, 3 warnings
Please check you have setup the license correctly.
During simulation, when I give a clock i/p to input A, it appears after a lot of delay in the same line. This is making my output go wrong. Is there a place I can set this delay as 0?
You should NOT set the delay to 0. This is the combinational logic delay and should be preserved. You need to check out what is the maximum delay time for your critical path. Also you need to check what is your current cycle time setting. Translate that cycle time to working frequency and you should be able to figure out the problem.
How to save the simulation waveform result?
You should submit the
value
change dump file (*.vcd), not *.vwf.
The *.vcd file contains both input waveform as well as the
simulation output. You can save the result by performing the following steps:
- Open Processing -> Simulation Report
- Right click on Simulator -> Simulation Waveforms, and select
Save Current Report Section As...
- Uncheck the "Add file to current project,"
and select Value Change Dump File (*.vcd) from the Save as type
dropdown menu.
You should also include a short note describing the list of
instructions (both function and input values) tested in this waveform file.
What is a simulation force file?
A simulation force file is an input simulation file
with different input traces for each input port. It can be designed either from the waveform designer, or
written in the Verilog functional simulation syntax. Note that
if you are using Verilog functional simulation, you will have to
make sure that you incorporate the device delay information when
you perform the simulation.
How to check register values during simulation?
You
will not be able to check additional register
values during/after simulation. However you
should be able to
select registers from the node finder. Here's how:
- Click on Node Finder
- Click on the "..." button right next to the "Look in:"
textbox
- Select the module that contains the register you want to
check from Select Hierarchy Level, and click OK
- Select Pins: all & Registers: post-fitting from the Filter
dropbox, and click on List button.
- You should be able to find the register you are looking for!