Instructors

Jacob Eapen

Associate Lecturer

Office: 3612 Engineering Hall. Phone no. 265-3789

Email: eapen@cae.wisc.edu

Office Hours: TW 11:30 to 12:30; M 12:30 – 2:30. Or by appointment

Moazzam Chaudry

Teaching Assistant (Discussion. 601 and Lab section 301)

Office: B632 EH Phone no. 2654885

Email: chaudry@cae.wisc.edu

Office Hours: R 12:10pm to 1:10pm or by appointment

Suniti Mandelia

Teaching Assistant (Lab section 302)

Office: B632 EH Phone no. 2569429

Email: mandelia@cae.wisc.edu

Office Hours: TBA

Course Information

The course has 3 components

1) Lectures (lec.1) on MTWR 10:20 to 11:10 in Room 3534

2) Lab Lectures (Disc. 601) on certain Thursdays from 1:10 to 2:00. (Room No. 3534)

3) ECE376 Lab which meets 5 times in the year (see Lab and Disc. Schedule)

i. Lab 301 on Wed. 2:35 – 5:35 in Room 3542 EH

ii. Lab 302 on Tue. 2:35 – 5:35 in Room 3542 EH

Attendance is required for all three components.

Homework

Approximately two homework’s will be assigned weekly and will be due on Tuesday / Thursday (as indicated). Late HW will not be accepted and one lowest HW score may be dropped.

Quizzes

Approximately 3 (20 minute) quizzes will be given in class, based on material from the HW.

Exams

There will be 3 exams of 2 hour duration on the following days

Tuesday, July 2^nd at 7:00 pm in Room 3534 EH

Wednesday, July 24^th at 7:00 pm in Room 3534 EH

Wednesday, August 7^th at 7:00 pm in Room 3534 EH

Grading Policy

The grade for the course will be based on

3 Exams @ 15% each 45%

Laboratory 25%

Homework 15%

Quizzes 10%

Class Participation 5%

Total 100%

Class participation

This will be determined by your attendance in class and participating group exercises.

Textbook

The required textbooks for this course are

1) Fundamentals of Electric Circuits by J.R Cogdell

2) ECE 376 Lecture notes on Digital Logic Circuits by Stremler and Marleau (Available at Bob’s copy shop).

In addition a good reference book for this course is

Electric Circuits by Nilsson and Riedel.

Course Outline (This is a tentative schedule of the material that will be covered in class)

Week	Date	Topic	Reading
1.	June 17	Introduction to course, current and voltage, KVL, KCL.	1.1 – 1.5
	June 18	Sign Conventions, Resistance, Ohm’s Law, series and parallel resistors, voltage and current dividers	1.6 – 1.7
	June 19	Analysis of D.C circuits: Superposition, Thevenin model	2.1 – 2.2
	June 20	(Analysis cont’d) Thevenin and Norton equivalent circuits , source transformations,	2.1 – 2.2
2	June 24	Maximum Power transfer theorem, Node and Mesh Analysis	2.3 – 2.4
	June 25	Quiz 1. More on Node-voltage analysis and Loop-Current analysis	2.3 – 2.4
	June 26	More on Node –voltage analysis and Loop Current analysis (dependent sources), Into. to Op-amps.	2.3 – 2.4
	June 27	Op-amps, feedback, virtual ground concept, basic Op-amp circuits	Notes (or reference)
3	July 1	More on Op-amp circuits, Op-amp saturation, Some applications	Notes (or reference)
	July 2	Review for Exam 1. Exam will in held in the evening at 7:00 p.m. in Room. 3534 EH
	July 3	Capacitor and Inductors; Excitaton by Sinusoids	3.1
4	July 8	Intro. to complex numbers, Phasor representation, using phasors to add sinusoids.	Notes and 4.1 – 4.2
	July 9	Impedance, admittance, DC methods applied to AC circuits.	4.3
	July 10	Phasor representation of AC circuits	4.4
	July 11	Quiz no. 2; More on AC circuits.
5	July 15	1^st order RC, and LR filters.	5.4
	July 16	Op-amp filters. And applications	Notes
	July 17	Average, real and reactive power in AC circuits	6.1
	July 18	Complex power in AC circuits	6.2
6	July 22	Ideal Transformers, maximum power transfer	6.3
	July 23	Review for Exam 2.
	July 24	Exam will in held in the evening at 7:00 p.m. in Room. 3534 EH
	July 25	Boolean algebra and basics of digital logic.	Notes on digital
7	July 29	Combinational logic circuits.	Notes on digital
	July 30	Karnaugh maps and Reduction techniques	Notes on digital
	July 31	Arithmetic Operation Circuits, Mux, DeMux and code converters (Timing analysis)	Notes on digital and class notes
	Aug 1	Quiz 3; Flip-Flops. (S-R, D, T, J-K)	Notes on digital
8	Aug 5	Sequential circuit analysis and design	Notes on digital
	Aug 6	CPLD’s (Programmable logicc) and applications	Class notes
	Aug 7	Review and Exam 3. Exam will in held in the evening at 7:00 p.m. in Room. 3534.
	Aug 8	Course assessment and feedback.