ECE 553: Testing and Testable Design of Digital Systems,
Fall 2011-2012

Kewal K. Saluja

saluja@engr.wisc.edu
Lecture Hours and Location: TR 11:00-12:15, Room 2121 Mechanical Engineering

(Optional) Discussion Session and Location:
Tuesday 4:00-5:00, Room 2540 Engineering Hall
   Instructor Office Hours:
T 2:00-3:30;
W 2:00-3:00;
and Other days and times by appointments only.
Room 4611 Engg. Hall
   Teaching Assistant and office hours:

Spencer Millican
smillican@wisc.edu
Office Hours : Monday 2:30-3:30 PM
Location : Room 3634 EH
Course Material (PDF files)
  • Outline
  • Conduct
  • Reading List
  • Reference material
  • Reserve in Wendt
  • Test tools for the course
    • DISCUSSION MATERIAL
    PROJECT
    Correction to the text:
  • Corrections
    Class Schedule and material covered in the lectures - Fall 2011-2012 
    
9/6   
  •  Lecture 1 in pdf (6 slides per page)    
       
  •  Lecture 1 in powerpoint           
	Motivational material
	Course material and its sources
	Course conduct and course outline
	Introductory section (from the text - Chapter 1)
     		- VLSI realization process,
		- Contract between design house and fab house
		- verification v/s testing
            - Need for testing
		- Levels of testing and rule of 10
		- Cost and role of testing
		
	Read: Chapter 1 of the text and papers # 1 from the notes
	
9/8   
  •  Lecture 2 in pdf (6 slides per page)

  •  Lecture 2 in powerpoint           
	Test process and test equipment (from the text - Chapter 2)
		- Objective
		- Types of testing          
			- Sub-types of testing 
		- Functional test
		- Focus: gate level design, Chip level testing
		- Test equipment (self study)

  •  Selected slides for Lecture 2 in pdf (6 slides per page)

  •  Lecture 3 in powerpoint           
	Test Economics
		- Objective
		- Basics of economics
		- Economics of Design for Testability (DFT)
		- Yield equation

	Distributed Homework set 1 (pdf file) 

	Available Netlist description of Circuit 1 for Problem 1.7 of Homework set 1  
      Available Netlist description of Circuit 2 for Problem 1.7 of Homework set 1  

	Assignment #1 Due Thursday 9/22 in class.


    

9/13 
 Test Economics (Contd.)
            - Yield equation
		- Yield, defect, coverage and relation between these
		- Parameter estimation
		- Impact on cost at higher levels (such as board level)


  •  Selected slides for Lecture 3 and 4 in pdf (6 slides per page)
    
  •  Lecture 4 in powerpoint     
      
	Logic Modeling
		- Objective
		- Logic modeling
		- Model types
		- Models a different levels of abstractions
		- Models, definitions, and examples
		- Hierachical
		- combinational - program, cubes

9/15
  Logic Modeling (contd.)
		- combinational -  cubes, BDDs, program
		- sequential - timeframe expansion
		- structural
		- External and internal models
            - general concepts and definitions


  •  Selected slides for Lecture 4, 5 in pdf (6 slides per page)
  
  •  Lecture 4, 5 in powerpoint           
	Fault Modeling
		- Why?
		- Defect statistics
		- Common fault models
		- Single stuck-at fault - and its justification


    

9/20 

International Test Conference (ITC) is being held this week. 

 Fault Modeling (continued)
		- What is a test, how to find a test for a fault
		- Fault detection and redundancy
		- Fault list reduction 
           	- fault equivalences 
		- fault dominance, checkpoint faults


9/22     Homework #1 Due today

	Distributed Homework set 1 solution (pdf file) 

  Fault Modeling (continued)
		- fault dominance, checkpoint faults
		- Some important theorems
		- transistor faults


  •  Selected slides for Lectures 5 and 6 in pdf (6 slides per page)
  
  •  Lecture 5, 6 in powerpoint           	
      Logic Simulation
            - what is simulation
		- What is simulation
		- Design verification
		- Circuit and delay modeling
		- Gate evaluation and determining signal values
		- True value simulation algorithms
		- Compile-code simulation
		- Event-driven simulation


  •  Selected slides for Lectures 6, 7 and 8 in pdf (6 slides per page)

  •  Lecture 6, 7, 8 in powerpoint           
	Fault Simulation
		- Basics, applications





    

9/27         
	Fault Simulation (contd.)
		- Basics, applications, fault simulator in design loop
		- Problem overview
		- Serial fault simulation - fault injection, 3-value coding
            - Parallel fault simulation
            - Fault simulation algorithms
                  - Deductive fault simulation

	Distributed Homework set 2 (pdf file) 
	Assignment #2 DUE Thursday 10/06 in class.


9/29
     	Fault Simulation (contd.)
          - Fault simulation algorithms
             - Deductive fault simulation
		 - Examples of serial, parallel, deductive fault simulators
		 - Concurrent simulation
		 - other simulators (e.g. parallel pattern single fault)
          - statistical fault simulation method (sampling)


  •  Selected slides for Lecture 8 and 9 in pdf (6 slides per page) 

  •  Lecture 8, 9 in powerpoint           
	ATPG Basics
		- Structural v/s functional testing
	

    

10/4

 ATPG Basics (contd.)
		- Definitions
		- Types of algorithms
		- Notation and algebra
		- Conditions for finding tests
		- Random and exhaustive
		- Method of Boolean difference
		- Path sensitization method
            - complixity issue

   Selected slides for Lecture 9 and 11 in pdf (6 slides per page)

  •  Lecture 9-11 in powerpoint           	
       Test Generation - combinational circuits ATPG
		- Introduction
		- Definitions, notation and D-calculus



10/6     Homework 2 Due today
           	
       Test Generation - combinational circuits ATPG (contd.)
		- Definitions, notation and D-calculus
		- D-Algorithm and an example 
		- Podem



    

10/11 
	Test Generation - combinational circuits ATPG (contd.)
		- Podem


  •  Selected slides for Lecture 11 to 13 in pdf (6 slides per page)
	ATPG systems and testability analysis

  •  Lecture 11-13 in powerpoint           


  ATPG systems and testability analysis (contd.)
	       ATPG systems 	- Phase 1
			- Phase 2 issues
				- Fault simulation efficiency
				- Increasing test generation efficiency
				- Compaction - dynamic and static
                        - etc.

	Distributed Homework set 2 solution(pdf file) 

	Distributed Homework set 3 (pdf file) 
	Assignment #3 DUE Thursday 10/20 in class.


10/13
  ATPG systems and testability analysis (contd.)
          - comments on compaction etc.

           Testability measures
			- Purpose and origin
			- SCOAP measure: combinational
			- SCOAP measure: Sequential


    

10/18

           Testability measures (contd.)
			- SCOAP measure: Sequential
			- Applications of SCOAP
            Comments - estimating the size of a test set for a circuit


  •  Selected slides for Lecture 13 to 15 in pdf (6 slides per page)

  •  Lecture 13-15 in powerpoint           	

    Sequential Circuit ATPG
		- Motivation
		- Time frame expansion approach to ATPG
		- An example generating test sequence
			5 value v/s 9 value logic
		- Complexity
		- Acyclic and cyclic circuits

10/20  Homework 3 Due today

  Sequential Circuit ATPG (contd.)
		- Acyclic and cyclic circuits
		- ATPG systems
		- reverse time test generation
		- FASTEST - forward time test generation
            - Comments on FASTEST 
		- forward and reverse time test generation
      	- Simulation based test generators
		       CONTEST and genetic methods
		- comments on ATPG systems and testability measures

 

  Distributed Homework set 3 solution(pdf file)      
  Distributed Homework set 4 (pdf file) 
  Assignment #4 DUE Thursday 11/03 in class.



    

10/25
    Sequential Circuit ATPG (contd.)
      	- Simulation based test generators
		       CONTEST and genetic methods
		- comments on ATPG systems and testability measures


  •  Selected slides for Lectures 16 and 17 in pdf (6 slides per page)

  •  Lecture 16, 17 in powerpoint           	
        Checking experiment approach to testing
		- Introduction
            - Theory - model, fault model, synchronizing sequence
                       homing sequence, distinguishing sequence 
        




10/27
  Checking experiment approach to testing (contd.)
		- Theory - 
                       homing sequence, distinguishing sequence 
                       distinguishing sequence comments
		- design of checking sequence
		- complexity


  •  Selected slides for Lectures 17 and 19 in pdf (6 slides per page)

  •  Lecture 17-19 in powerpoint           
 
   Functional Testing - Introduction




    

11/1 
  Functional Testing (contd.)
		- Structure independent and  dependent testing of            
                       combinational and sequential circuits
		- Organization/architecture dependent testing
		- Methods and principles of testing microprocessors
		- Microprocessor testing

11/3       Homework #4 Due today
  Distributed Homework set 4 solution(pdf file)  

  Functional Testing (contd.)
		- Microprocessor testing



  •  Selected slides for Lectures 20 and 21 in pdf (6 slides per page)

  •  Lecture 20, 21 in powerpoint           
	Memory Testing
		- Motivation
		- Memory Model
 


    	

11/8


     Memory Testing (contd.)
            - Fault models
		- Test algorithms - March tests
		- NPSF models and test methods

11/10   MIDTERM EXAM  	(Note it is an evening exam)
         Time: 7:15PM  Room 1153 Mechanical Engineering 


	Syllabus for the Midterm Exam (PDF file) 


An Old Midterm exam and solution:
	Midterm exam (year 2010 fall) PDF file 
	Midterm Exam Solution (year 2010 fall) PDF file 

	Distributed Homework set 5 (pdf file) 
	Assignment #5 DUE Tuesday, Nov. 22 to the TA by 3:00PM


    

11/11 Friday - PROJECT distribution
	
  •  Project Description

	Midterm exam and solution:
	Midterm exam (year 2011 fall) PDF file) 
	Midterm Exam Solution (year 2011 fall) PDF file) 


    

11/15  Midterm 2011  returned in class:  Av = 68,  
                    std dev = 3.7.
       Distribution: 
                  80-89   4;
                  70-79   8;
                  60-69   4;
                  50-59   6;
                    -49   2;


   Memory Testing (contd.)
		- NPSF models and test methods


  •  Selected slides for Lectures 21 in pdf (6 slides per page)

  •  Lecture 21 in powerpoint           


	Iddq Testing
		- Introduction
		- Faults and fault detection
		- Instrumentation issues
		- Sematech study
		- Future of Iddq testing
		
	Comments on limitations and future of Iddq Testing


  •  Selected slides for Lectures 21 and 22 in pdf (6 slides per page)

  •  Lecture 21, 22 in powerpoint  
         
	Design for Testability (DFT)
		- Introduction 

 

11/17 
	Design for Testability (DFT) (Contd.)
		- Introduction 
            - Ad hoc DFT methods
            - Structured full-scan techniques
			- What is scan
			- Scan methods
			- mux and LSSD based scan
		- test generation and test application
		- Scan automation	
		- Scan overhead 

	



    


11/22   There will be No Lecture today (I will be away at the Asian Test Symposium)
        Homework 5 is due today - submit to the TA by 3:00 PM


   Asian Test Symposium - I will be away 

	
	Distributed Homework set 5 Solution (pdf) 	
	Distributed Homework set 6 (pdf file) 
	Assignment #6 DUE Thursday 12/8 


11/24   Thanksgiving day - No classes (Classes Resume November 28)




    

11/29
  Design for Testability (DFT) - Contd.
		- Scan automation	
		- Scan overhead 


  •  Selected slides for Lectures 23 and 24 in pdf (6 slides per page)

  •  Lecture 23 and 24 in powerpoint  


	  Design for Testability (DFT-2) 
		- Partial scan 
            - Scan flip-flop selection: cycle breaking method
		- test generation and test application with partial scan
		- Scan methods and issues
			mux based, scan set, random access scan, LSSD, etc.

12/1
	  Design for Testability (DFT-2) - Contd.
		- Scan methods and issues
			mux based, scan set, random access scan, LSSD, etc.
			

  •  Selected slides for Lectures 24 and 25 in pdf (6 slides per page)

  •  Lecture 24 and 25 in powerpoint

         Built-in Self-Test (BIST) 
		- economics, advantages and shortcomings
		- Pattern generation
			Theory of LFSRs - characteristic and primitive polynomials



    
		

12/6
     Built-in Self-Test (BIST) (contd.)
            - Pattern generation
			Theory of LFSRs - characteristic and primitive polynomials
            - Weighted pattern generation and other alternatives
		- response compaction 
			Basics

12/8  	 Project Final Report due today (Thursday December 8) 

     Built-in Self-Test (BIST) (contd.)
		- response compaction 
			Basics, LFSR, MISR, Transition counting
            - aliasing and other basic issues


  •  Selected slides for Lectures 27 and 28 in pdf (6 slides per page)

  •  Lecture 27 and 28 in powerpoint

	  BIST architectures

	Distributed Homework set 6 Solution (pdf) 
	Distributed Homework set 7 (pdf file) 
	Assignment #7 DUE Thursday 15 in class 



    


12/13  BIST architectures (contd.)
		-Test per scan and test per clock 
		-BILBO, MISR and associated architectures


  •  Selected slides for Lectures 29 in pdf (6 slides per page)

  •  Lecture 29 in powerpoint

      Boundary Scan - Introduction
         Architecture, cell desing, TAP controller

     Course evaluation (last 10 minutes)


     Distributed Homework set 7 Solution (pdf) 

12/15  Homework #7 Due today 


  •  Challenges in testing - Selected problems (.ppt file)




    

12/17 Saturday:  Final Exam  2:45 PM  Room 2540 Engineering Hall (2 hours exam)   

	Syllabus for the Final Exam (PDF file) 

Old exam and solution: 
Final 2010 exam and solution for you:

	Exam (year 2010 fall) PDF file 
	Solution to exam (year 2010 fall) PDF file 


Final 2011 exam and solution:

	This exam (year 2011 fall) PDF file 
	Solution to this exam (year 2011 fall) PDF file