ECE 553: Testing and Testable Design of Digital Systems,
Fall 2014-2015

Kewal K. Saluja

saluja@engr.wisc.edu
--- THIS SITE WILL BE UPDATED ON REGULAR BASIS DURING THE SEMESTER ---
Lecture Hours and Location: TR 11:00-12:15, Room 3126 Mechanical Engineering


   Instructor Office Hours:
M 2:00-3:00;
T 2:00-3:00;
W 2:00-3:00;
and Other days and times by appointments only.
Room 4611 Engg. Hall
   Project Manager:
Course Material (PDF files)
  • Cover Page
  • Goals and Topics
  • Outline
  • Conduct
  • Reading List
  • Reference material
  • Reserve in Wendt

  • Reading Material links
  • Links to books reserve in the library
  • William and Brown Paper
  • Kelsey, Saluja and Lee Paper
  • Hennie Paper in pdf format
  • Linear feedback shift register notes in pdf format
  • Test tools for the course prepared by Saluja and Kime
  • Yao, Saluja and Ramanathan Survey paper
  • Spencer Millican and Kewal Saluja - a paper due to appear in the Journal of Electronic Testing: Theory and Applications
  • Touba paper


  • PROJECT
    Correction to the text:
  • Corrections
    Class Schedule and material covered in the lectures - Fall 2014-2015
    9/2
      
  • Lecture 1 in pdf (6 slides per page)
  • Lecture 1 in powerpoint Motivational material Course material and its sources Course conduct and course outline Introductory section (from the text - Chapter 1) - VLSI realization process, - Contract between design house and fab house - verification v/s testing - Need for testing - Levels of testing and rule of 10 - Cost and role of testing Read: Chapter 1 of the text and papers # 1 from the notes 9/4
  • Lecture 2 in pdf (6 slides per page)
  • Lecture 2 in powerpoint Test process and test equipment (from the text - Chapter 2) - Objective - Types of testing - Sub-types of testing - Functional test - Focus: gate level design, Chip level testing - Test equipment (self study)
  • Selected slides for Lecture 2 in pdf (6 slides per page)
  • Lecture 3 in powerpoint Test Economics - Objective - Basics of economics Distributed Homework set 1 (pdf file) Available Netlist description of Circuit 1 for Problem 1.7 of Homework set 1 Available Netlist description of Circuit 2 for Problem 1.7 of Homework set 1 Assignment #1 Due Thursday 9/18 in class.
    9/9 Test Economics (Contd.) - Yield equation - Yield, defect, coverage and relation between these - Parameter estimation - Impact on cost at higher levels (such as board level)
  • Selected slides for Lecture 3 and 4 in pdf (6 slides per page)
  • Lecture 4 in powerpoint Logic Modeling - Objective - Logic modeling - Model types - Models a different levels of abstractions - Models, definitions, and examples - Hierachical
  • Example of internal reperentation of a circuit data structure for Lecture 4 (pdf file) 9/11 Logic Modeling (contd.) - combinational - cubes, BDDs, program - sequential - timeframe expansion - structural - External and internal models - general concepts and definitions
  • Selected slides for Lecture 4, 5 in pdf (6 slides per page)
  • Lecture 4, 5 in powerpoint Fault Modeling - Why?
    9/16 I will be away today - No class 9/18 Homework #1 Due today Fault Modeling - Why? - Defect statistics - Common fault models - Single stuck-at fault - and its justification - What is a test, how to find a test for a fault - Fault detection and redundancy - Fault list reduction
    9/23 Fault Modeling (contd.) - fault equivalences - fault dominance, checkpoint faults - Some important theorems - transistor faults
  • Selected slides for Lectures 5 and 6 in pdf (6 slides per page)
  • Lecture 5, 6 in powerpoint Logic Simulation - What is simulation - Design verification - Circuit and delay modeling - Gate evaluation and determining signal values - True value simulation algorithms - Compile-code simulation - Event-driven simulation 9/25
    9/30 10/2
    10/7 10/9
    10/14 10/16
    10/21 10/23
    10/28 10/30
    11/4 11/6
    11/11 MIDTERM EXAM (Note it is an evening exam) Time: 7:15PM Room TBD 11/13
    11/18 11/20
    11/25 11/27 Thanksgiving day - No classes (Classes Resume December 1)
    12/2 12/4
    12/9 12/11
    12/14 Sunday: Final Exam 12:25 PM Room TBD