ECE 553: Testing and Testable Design of Digital Systems,
Fall 2014-2015

Kewal K. Saluja

saluja@engr.wisc.edu
--- THIS SITE WILL BE UPDATED ON REGULAR BASIS DURING THE SEMESTER ---
Lecture Hours and Location: TR 11:00-12:15, Room 3126 Mechanical Engineering


   Instructor Office Hours:
M 2:00-3:00;
T 2:00-3:00;
W 2:00-3:00;
and Other days and times by appointments only.
Room 4611 Engg. Hall
   Project Manager:
Course Material (PDF files)
  • Cover Page
  • Goals and Topics
  • Outline
  • Conduct
  • Reading List
  • Reference material
  • Reserve in Wendt

  • Reading Material links
  • Links to books reserve in the library
  • William and Brown Paper
  • Kelsey, Saluja and Lee Paper
  • Hennie Paper in pdf format
  • Linear feedback shift register notes in pdf format
  • Test tools for the course prepared by Saluja and Kime
  • Yao, Saluja and Ramanathan Survey paper
  • Spencer Millican and Kewal Saluja - a paper due to appear in the Journal of Electronic Testing: Theory and Applications
  • Touba paper


  • PROJECT
    Correction to the text:
  • Corrections
    Class Schedule and material covered in the lectures - Fall 2014-2015
    9/2
      
  • Lecture 1 in pdf (6 slides per page)
  • Lecture 1 in powerpoint Motivational material Course material and its sources Course conduct and course outline Introductory section (from the text - Chapter 1) - VLSI realization process, - Contract between design house and fab house - verification v/s testing - Need for testing - Levels of testing and rule of 10 - Cost and role of testing Read: Chapter 1 of the text and papers # 1 from the notes 9/4
  • Lecture 2 in pdf (6 slides per page)
  • Lecture 2 in powerpoint Test process and test equipment (from the text - Chapter 2) - Objective - Types of testing - Sub-types of testing - Functional test - Focus: gate level design, Chip level testing - Test equipment (self study)
  • Selected slides for Lecture 2 in pdf (6 slides per page)
  • Lecture 3 in powerpoint Test Economics - Objective - Basics of economics Distributed Homework set 1 (pdf file) Available Netlist description of Circuit 1 for Problem 1.7 of Homework set 1 Available Netlist description of Circuit 2 for Problem 1.7 of Homework set 1 Assignment #1 Due Thursday 9/18 in class.
    9/9 Test Economics (Contd.) - Yield equation - Yield, defect, coverage and relation between these - Parameter estimation - Impact on cost at higher levels (such as board level)
  • Selected slides for Lecture 3 and 4 in pdf (6 slides per page)
  • Lecture 4 in powerpoint Logic Modeling - Objective - Logic modeling - Model types - Models a different levels of abstractions - Models, definitions, and examples - Hierachical
  • Example of internal reperentation of a circuit data structure for Lecture 4 (pdf file) 9/11 Logic Modeling (contd.) - combinational - cubes, BDDs, program - sequential - timeframe expansion - structural - External and internal models - general concepts and definitions
  • Selected slides for Lecture 4, 5 in pdf (6 slides per page)
  • Lecture 4, 5 in powerpoint Fault Modeling - Why?
    9/16 I will be away today - No class 9/18 Homework #1 Due today Fault Modeling - Why? - Defect statistics - Common fault models - Single stuck-at fault - and its justification - What is a test, how to find a test for a fault - Fault detection and redundancy - Fault list reduction
    9/23 Fault Modeling (contd.) - fault equivalences - fault dominance, checkpoint faults - Some important theorems - transistor faults
  • Selected slides for Lectures 5 and 6 in pdf (6 slides per page)
  • Lecture 5, 6 in powerpoint Logic Simulation - What is simulation - Design verification - Circuit and delay modeling 9/25 Logic Simulation (contd.) - Gate evaluation and determining signal values - True value simulation algorithms - Compile-code simulation - Event-driven simulation
  • Selected slides for Lectures 6, 7 and 8 in pdf (6 slides per page)
  • Lecture 7, 8 in powerpoint Fault Simulation - Basics, applications, fault simulator in design loop - Problem overview - Serial fault simulation - fault injection, 3-value coding - Parallel fault simulation
  • Sheet for example Parallel Faullt Simulation (pdf file) Distributed Homework set 1 solution (pdf file) Distributed Homework set 2 (pdf file) Assignment #2 DUE Thursday 10/2 in class.
    9/30 Fault Simulation (continued) - Serial fault simulation - fault injection, 3-value coding - Parallel fault simulation - Fault simulation algorithms - Deductive fault simulation - Examples of serial, parallel, deductive fault simulators - Concurrent simulation - other simulators (e.g. parallel pattern single fault) - statistical fault simulation method (sampling) 10/2 Homework 2 Due today Distributed Homework set 2 solution (pdf file)
  • Selected slides for Lecture 8 and 9 in pdf (6 slides per page)
  • Lecture 8, 9 in powerpoint ATPG Basics - Structural v/s functional testing - Definitions - Types of algorithms - Notation and algebra - Conditions for finding tests - Method of Boolean difference - Random and exhaustive - Path sensitization method - complixity issue Selected slides for Lecture 9 and 11 in pdf (6 slides per page)
  • Lecture 9-11 in powerpoint Test Generation - combinational circuits ATPG - Introduction - Definitions, notation
    10/7 Test Generation - combinational circuits ATPG (contd.) - Definitions, notation and D-calculus - D-Algorithm and an example Distributed Homework set 3 (pdf file) For Problem 8 the circuit n432 and 10 test vectors for it are also avialable through the following link Circuit for Problem 8 n432 circuit in UW format Test vectors for Problem 8 10 test vectors for n432 circuit Assignment #3 DUE Thursday 10/16 in class. 10/9 Test Generation - combinational circuits ATPG (contd.) - Podem - Comments on the algorithms
  • Selected slides for Lecture 11 to 13 in pdf (6 slides per page)
  • Lecture 11-13 in powerpoint ATPG systems and testability analysis ATPG systems - Phase 1 - Phase 2 issues - Fault simulation efficiency - Increasing test generation efficiency - Compaction - dynamic and static - comments on compaction etc.
    10/14 ATPG systems and testability analysis (contd.) - Compaction - dynamic and static - comments on compaction etc. Testability measures - SCOAP measure: combinational - SCOAP measure: Sequential - Applications of SCOAP 10/16 Homework 3 Due today Testability measures (contd.) - SCOAP measure: Sequential Comments - estimating the size of a test set for a circuit
  • Selected slides for Lecture 13 to 15 in pdf (6 slides per page)
  • Lecture 13-15 in powerpoint Sequential Circuit ATPG - Motivation - Time frame expansion approach to ATPG - An example generating test sequence 5 value v/s 9 value logic - Complexity - Acyclic and cyclic circuits Distributed Homework set 3 solution(pdf file) Distributed Homework set 4 (pdf file) Assignment #4 DUE Tuesday 11/04 in class. - Note due Tuesday
    10/21 Sequential Circuit ATPG (contd.) - ATPG systems - reverse time test generation - FASTEST - forward time test generation - Read paper
  • Sequential Test Generation by FASTEST in pdf - Simulation based test generators CONTEST and genetic methods - comments on ATPG systems and testability measures
  • Selected slides for Lectures 16 and 17 in pdf (6 slides per page)
  • Lecture 16, 17 in powerpoint Checking experiment approach to testing - Introduction International Test Conference (ITC) is being held this week. 10/23 Checking experiment approach to testing (contd.)
  • Hennie Paper in pdf format - Theory - homing sequence, distinguishing sequence distinguishing sequence comments - design of checking sequence - complexity
    10/28 Checking experiment approach to testing (contd.) - design of checking sequence - complexity
  • Selected slides for Lectures 17 and 19 in pdf (6 slides per page)
  • Lecture 17-19 in powerpoint Functional Testing - Introduction - Structure independent and dependent testing of combinational and sequential circuits 10/30 Functional Testing (contd.) - Structure independent and dependent testing of combinational and sequential circuits
  • Funcitonal testing - ref Abramovici - pdf file - Organization/architecture dependent testing - Methods and principles of testing microprocessors
  • Microprocessor testing - ref Abramovici - pdf file - Microprocessor testing
    11/4 Homework #4 Due today Functional Testing (contd.) - Microprocessor testing
  • Selected slides for Lectures 20 and 21 in pdf (6 slides per page)
  • Lecture 20, 21 in powerpoint Memory Testing - Motivation - Memory Model - Fault models - Test algorithms - March tests Distributed Homework set 4 solution(pdf file) 11/6 Memory Testing (contd.) - Test algorithms - March tests - NPSF models and test methods
    11/11 Lecture hour will be used for discussion MIDTERM EXAM (Note it is an evening exam) Time: 7:15PM Room 2535 Engineering Hall Project posting
  • Project Description Syllabus for the Midterm Exam (PDF file) An Old Midterm exam and solution: Midterm exam (year 2013 fall) PDF file Midterm Exam Solution (year 2013 fall) PDF file Midterm exam and solution: Midterm exam (year 2014 fall) PDF file) Midterm Exam Solution (year 2014 fall) PDF file) 11/13 In class Project discussion
  • Selected slides for Lectures 21 in pdf (6 slides per page)
  • Lecture 21 in powerpoint Iddq Testing - Introduction - Faults and fault detection - Instrumentation issues - Sematech study - Future of Iddq testing Comments on limitations and future of Iddq Testing
  • Selected slides for Lectures 21 and 22 in pdf (6 slides per page)
  • Lecture 21, 22 in powerpoint Design for Testability (DFT) - Introduction - Ad hoc DFT methods Distributed Homework set 5 (pdf file) Assignment #5 DUE Tuesday 12/2 (in class).
    11/17 (Monday) Email your information to the Project Manager - please see the project description 11/18 You will be assigned circuit for your project Design for Testability (DFT) (contd.) - Introduction - Structured full-scan techniques - What is scan - Scan methods - mux and LSSD based scan - test generation and test application for scan circuits - Scan automation - Scan overhead 11/20 Design for Testability (DFT) (Contd.) - Scan overhead
  • Selected slides for Lectures 23 and 24 in pdf (6 slides per page)
  • Lecture 23 and 24 in powerpoint Design for Testability (DFT-2) - Partial scan - Scan flip-flop selection: cycle breaking method
    11/25 Project Progress and status report due - please email your report to the Project Manager Follow the instrutions provided in the project details Design for Testability (DFT-2) - Scan flip-flop selection: cycle breaking method - test generation and test application with partial scan - Scan methods and issues mux based, scan set, random access scan, LSSD, etc. - Scan issues - power issue
  • Selected slides for Lectures 24 and 25 in pdf (6 slides per page)
  • Lecture 24 and 25 in powerpoint Built-in Self-Test (BIST) - economics, advantages and shortcomings 11/26 (Wednesday) - Virtual chip distribution for the project 11/27 Thanksgiving day - No classes (Classes Resume December 1)
    12/2 Homework #5 Due today Solution available: Homework set 5 Solution (pdf file) Built-in Self-Test (BIST) (contd.) - economics, advantages and shortcomings - Pattern generation Theory of LFSRs - characteristic and primitive polynomials
  • External and Internal Exclusive-OR LFSR - pdf file
  • External Exclusive-OR LFSR - pdf file Distributed Homework set 6 (pdf file) Assignment #6 DUE Thursday 12/11 12/4 Built-in Self-Test (BIST) (contd.) - Pattern generation primitive polynomials, zero insertion - Weighted pattern generation and other alternatives - Response compaction LFSR, MISR - Aliasing and other basic issues
    12/9 Final Project Report Due Today (Tuesday December 9) Built-in Self-Test (BIST) (contd.) - Response compaction LFSR, MISR - Aliasing and other basic issues
  • Selected slides for Lectures 27 and 28 in pdf (6 slides per page)
  • Lecture 27 and 28 in powerpoint BIST architectures -Test per scan and test per clock -BILBO, MISR and associated architectures 12/11 Homework #6 Due today Solution available: Homework set 6 Solution (pdf)
  • Selected slides for Lectures 29 in pdf (6 slides per page)
  • Lecture 29 in powerpoint Boundary Scan - Introduction Architecture, cell desing, TAP controller
  • A Tutorial on VLSI Testing indcuding New Challanges (.ppts file) Course conclusion - Topics we did not cover and why - comments on future directions For online Course Evaluation please click on the link below
  • Course Evaluation Link or copy and past the following URL in your browser: https://aefis.engr.wisc.edu/
    12/14 Sunday: Final Exam 12:25 PM Room 3418 Engineering Hall (2 hours exam) Syllabus for the Final Exam (PDF file) Old exam and solution: Final 2013 exam and solution for you: Exam (year 2013 fall) PDF file Solution will be posted later Solution to exam (year 2013 fall) PDF file Final 2014 exam and solution: This exam (year 2014 fall) PDF file Solution to this exam (year 2014 fall) PDF file