9/3   
 Lecture 1 in pdf (6 slides per page)           
	Motivational material
	Course material and its sources
	Course conduct and course outline
	Introductory section (from the text - Chapter 1)
     		- VLSI realization process,
		- Contract between design house and fab house
		- verification v/s testing
            - Need for testing
		- Levels of testing and rule of 10
		- Cost and role of testing
		
	Read: Chapter 1 of the text and papers # 1 from the notes

	
9/8    
 Lecture 2 in pdf (6 slides per page)
	Test process and test equipment (from the text - Chapter 2)
		- Objective
		- Types of testing          
			- Sub-types of testing 
		- Functional test
		- Focus: gate level design, Chip level testing
		- Test equipment (self study)
 Selected slides for Lecture 2 in pdf (6 slides per page)
	Test Economics
		- Objective
		- Basics of economics
		- Economics of Design for Testability (DFT)
		- Yield equation


9/10   Test Economics (Contd.)
		- Yield, defect, coverage and relation between these
		- Parameter estimation
		- Impact on cost at higher levels (such as board level)

 Selected slides for Lecture 3 and 4 in pdf (6 slides per page)

	Logic Modeling
		- Objective
		- Logic modeling
		- Model types
		- Models a different levels of abstractions
		- Models, definitions, and examples
		- Hierachical
		- combinational - cubes, BDDs, program
		- sequential - timeframe expansion

	Distributed Homework set 1 (pdf file) 
	
	Assignment #1 Due Thursday 9/24 in class.


9/15  Logic Modeling (contd.)
		- structural
		- External and internal models
            - general concepts and definitions

 Selected slides for Lecture 4, 5 in pdf (6 slides per page)

	Fault Modeling
		- Why?
		- Defect statistics
		- Common fault models
		- Single stuck-at fault - and its justification


9/17   Starting today we will be meeting in Room 1152 Mechanical Engineering

     Fault Modeling (continued)
		- What is a test, how to find a test for a fault
		- Fault detection and redundancy
		- Fault list reduction 
           	- fault equivalences 
		- fault dominance, checkpoint faults



9/22       
     Fault Modeling (continued)
		- fault dominance, checkpoint faults
		- Some important theorems
		- transistor faults

 Selected slides for Lectures 5 and 6 in pdf (6 slides per page)
	
      Logic Simulation
            - what is simulation
		- What is simulation
		- Design verification
		- Circuit and delay modeling
		- Gate evaluation and determining signal values
		- True value simulation algorithms
		- Compile-code simulation
		- Event-driven simulation

	Distributed TESTCAD Toolset Manual (pdf file)

	


9/24    Homework #1 Due today

	Distributed Homework set 1 solution (pdf file) 

      Logic Simulation (contd.)
		- Event-driven simulation
            
 Selected slides for Lectures 6, 7 and 8 in pdf (6 slides per page)

	Fault Simulation
		- Basics, applications, fault simulator in design loop
		- Problem overview
		- Serial fault simulation - fault injection, 3-value coding
            - Parallel fault simulation

	Distributed Homework set 2 (pdf file) 
	Assignment #2 DUE Tuesday 10/06 in class.


9/29	Fault Simulation (contd.)
          - Fault simulation algorithms
             - Parallel fault simulation
             - Deductive fault simulation
		 - Examples of serial, parallel, deductive fault simulators
		 - Concurrent simulation
		 - other simulators (e.g. parallel pattern single fault)
          - statistical fault simulation method (sampling)



10/1	Fault Simulation (contd.)
	      - other simulators (e.g. parallel pattern single fault)
		- statistical fault simulation method (sampling)

 Selected slides for Lecture 8 and 9 in pdf (6 slides per page)
	ATPG Basics
		- Structural v/s functional testing
		- Definitions
		- Types of algorithms
		- Notation and algebra
		- Conditions for finding tests
		- Random and exhaustive
		- Method of Boolean difference
		- Path sensitization method
            - complixity issue



10/6  Homework 2 Due today

  Selected slides for Lecture 9 and 11 in pdf (6 slides per page)
	
       Test Generation - combinational circuits ATPG
		- Introduction
		- Definitions, notation and D-calculus
		- D-Algorithm   

	Distributed Homework set 2 solution(pdf file) 

	Distributed Homework set 3 (pdf file) 
	Assignment #3 DUE Tuesday 10/20 (new date 10/22) in class.


10/8   Test Generation - combinational circuits ATPG (contd.)
            - D-Algorithm example
		- Podem

 Selected slides for Lecture 11 to 13 in pdf (6 slides per page)
	ATPG systems and testability analysis



10/13  ATPG systems and testability analysis (contd.)
	       ATPG systems 	- Phase 1
			- Phase 2 issues
				- Fault simulation efficiency
				- Increasing test generation efficiency
				- Compaction - dynamic and static
                        - etc.



10/15 	Testability measures
			- Purpose and origin
			- SCOAP measure: combinational
			- SCOAP measure: Sequential
			- Applications of SCOAP
            Comments - estimating the size of a test set for a circuit

 Selected slides for Lecture 13 to 15 in pdf (6 slides per page)




10/20   ATPG systems and testability analysis (contd.)
			- Applications of SCOAP
            Comments - estimating the size of a test set for a circuit

	Sequential Circuit ATPG
		- Motivation
		- Time frame expansion approach to ATPG
		- An example generating test sequence
			5 value v/s 9 value logic
		- Complexity
		- Acyclic and cyclic circuits


10/22  Homework #3 Due today

	Distributed Homework set 3 solution(pdf file) 

Sequential Circuit ATPG (contd.)
		- ATPG systems
		- reverse time test generation
		- FASTEST
            - Comments on FASTEST 
		- forward and reverse time test generation
      	- Simulation based test generators
		       CONTEST and genetic methods
		- comments on ATPG systems and testability measures

	Distributed Homework set 4 (pdf file) 
	Assignment #4 DUE Tuesday, Nov. 3 in class.



10/27	Sequential Circuit ATPG (contd.)
      	- Simulation based test generators
			CONTEST and genetic algorithm
		- comments on ATPG systems and testability measures

 Selected slides for Lectures 16 and 17 in pdf (6 slides per page)
	
        Checking experiment approach to testing
		- Introduction
            - Theory - model, fault model, synchronizing sequence, homing sequence

        
10/29   Checking experiment approach to testing (contd.)
            - Theory - synchronizing sequence, homing sequence
		- Theory - distinguishing sequence comments
		- design of checking sequence
		- complexity

 Selected slides for Lectures 17 and 19 in pdf (6 slides per page)




	Syllabus for the Midterm Exam (PDF file)

	Distributed:  Old exam and solution: 
	An old exam (year 2008 fall) PDF file) 
	Solution to an old exam (year 2008 fall) PDF file) 




11/3    Homework #4 Due today
        Distributed Homework set 4 solution(pdf file) 

         International Test Conference in Austin - I will be away
         TA will conduct the exam review

   I will have extra office hours as follows:  
            Nov 6 - Friday  5:00-6:00  PM 
            Nov 9 - Monday 10:00-11:00 AM


11/5    International Test Conference in Austin - I will be away

      
11/9  MONDAY MIDTERM EXAM  	(Note it is an evening exam)
	Room: 1164 Mechanical Engineering (Lecture Room);  Time:  7:15 PM to 8:30 PM



	
11/10  Functional Testing 
		- Structure independent and  dependent testing of sequential circuits
		- Organization/architecture dependent testing
		- Methods and principles of testing microprocessors
		- Microprocessor testing

	Distributed Homework set 5 (pdf file) 
	Assignment #5 DUE Thursday, Nov. 19th in class.


11/11      Midterm 2009  will be returned tomorrow in class:  Av = 68,  

	Distribution: 	
			80+     2;
			60-79   5;
			40-69   3;

	Midterm exam and solution:
	Midterm exam (year 2009 fall) PDF file) 
	Midterm Exam Solution (year 2009 fall) PDF file) 

11/12   Functional Testing (contd.)
		- Microprocessor testing

 Selected slides for Lectures 20 and 21 in pdf (6 slides per page)
	Memory Testing
		- Motivation
		- Memory Model
		- Fault models

PROJECT distribution

	 Distributed Project Description (pdf file)



11/17   Memory Testing (contd.)
		- Test algorithms - March tests
		- NPSF models and test methods

 Selected slides for Lectures 21 and 22 in pdf (6 slides per page)

	Design for Testability (DFT)
		- Introduction 
            - Ad hoc DFT methods



11/19  Homework #5 Due today in class. 

       Design for Testability (DFT) (contd.)
            - Ad hoc DFT methods
            - Structured full-scan techniques
			- What is scan
			- Scan methods
			- mux and LSSD based scan
		- test generation and test application
		- Scan automation	
		- Scan overhead 

 Selected slides for Lectures 23 and 24 in pdf (6 slides per page)
	

	Solution available: Homework set 5 Solution (pdf file) 






11/24   Asian Test Symposium - I will be away


11/26 	Thanksgiving Recess  (Classes resume November 30)
        and  Asian test symposium 








12/1	  Design for Testability (DFT-2) 
		- Partial scan 
            - Scan flip-flop selection: cycle breaking method
		- test generation and test application with partial scan
		- Scan methods and issues
			mux based, scan set, random access scan, LSSD, etc.




12/3  



		


12/8 


12/10 



	

12/15 



12/17 Thursday:  Final Exam  10:05 AM  Room TBA