Description of the SRAM interface module in mdlring.v

Diagram of the signals used to interface with the Right SRAM bank.  The 'raddr', 'rdata', 'rread', and 'rwrite' signals are ouputs from the student module, and the 'rread_data' is an input to the student module.  All inputs to the interface module are registerd.  The 'rd', 'ra', 'rewb', 'roeb' and 'rceb' signals are driven exclusively by the interface module, and should NOT be connected to any student generated modules.  Note there are no bi-directional busses from the student module to the interface module.  The left SRAM bank operates identically.

The SRAM interface will complete one operation (ie: a read, a write, or nothing) each clock cycle of the input clock (from external clock generator). Writes take precedence over reads (so if both the 'read' and 'write' inputs to the interface module are asserted, the write will be performed and read will not). There are no restrictions on the order in which read and write operations can be performed.

The student designed processor module will need 4 output ports and 1 input port for accessing memory through the interface module.  Example module skeleton:

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module Proc(read, write, addr, data, read_data, … );

output read;
output write;
output [18:0] addr;
output [15:0] data;
input  [15:0] read_data;

…

endmodule
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