Frequently Asked Questions:

1 - Tutorial
   1.1 - Software Tutorial
       1.1.1 - Why do we need Xilinx Core Generator?
       1.1.2 - What are the differences between functional, post-synthesis, and timing simulations?
       1.1.3 - What is "work" library?
       1.1.4 - What is "Verilog" library in ModelSim?
       1.1.5 - What is a netlist (.edn and .edf) file?
       1.1.6 - What is logic (HDL) synthesis?
       1.1.7 - What is FPGA (netlist) implementation?
       1.1.8 - What is a UCF file?
   1.2 - Hardware Tutorial
       1.2.1 - What is a pod on a logic analyzer?
       1.2.2 - What is the configuration of these 4 pods?
       1.2.3 - Why is the pulse generator so important?
       1.2.4 - What is the maximum frequency of this generator?
       1.2.5 - We should pay more emphasis on hardware tutorial especially the logic analyzer!

2 - Mini-Project
   2.1 - Do we have to follow the organization shown in the handout?
   2.2 - What is the testbench?
   2.3 - How long is the CS (Chip Select) pulse asserted "1"?
   2.4 - What is RS232 or serial communication?
   2.5 - What is the Hyper Terminal?
   2.6 - What is the "enable" signal?
   2.7 - What is resynchronization?
   2.8 - Why do we need to do "resynchronization"?
   2.9 - Which bit is sent first?
   2.10 - If there is no data to Tx, what is the value of TxD?
   2.11 - Which part of the SPART should be tested first?
   2.12 - What else can go wrong?
   2.13 - How big are the received and transmit buffers?
   2.14 - Should we worry about buffer overflowing?
   2.15 - How wide are the start, stop bits?
   2.16 - How can the logic "0" and "1" be converted to RS232 signals?
   2.17 - How wide are the start, stop bits?
   2.18 - I was curious what you were indicating when you mentioned that the pulse periods should occur more than once per bit time. Do you recommend that the students implement some oversampling?
   2.19 - What setting (#data bits, #stop bits, #parity bits) is required for the miniproject?
   2.20 - In the receiver module, we have one big always @ (posedge clk) loop and the RxD changes within that. Isn't that the same as putting a DFF on the RxD...If not how do you do put a DFF on the RxD?
   2.21 - I worked on the ltring for our group, and I noticed that design manager doesn't like it when reset is assigned to the sw1 pushbutton pin. When I remove that assignment from the ring ucf file, DM runs the implementation with no errors. It seems to want to assign the reset signal to another specific pin (forgot which one exactly). It's strange because I just modified the given ring .v and .ucf files, and they worked ok for the tutorial design.
   2.22 - What to be included in the report?
   2.23 - Why do we need to grade their report with the Verilog source code?
   2.24 - "modularity" -- is that just that they didn't do the whole SPART in one big verilog source file?
   2.25 - "module interface" -- I'm not sure what you're looking for with this one...
   2.26 - "resynch" -- that's for synchronizing the incoming Rx line, right?
   2.27 - "sampling scheme" -- is that for using enable signals at 16x the baud rate to sample Rx in the middle of each bit?
   2.28 - Is it a bad thing to have a block: always @ (posedge SHIFT), where SHIFT is a user-defined signal generated in a different always block?...just wondering if that is a bad use of the language constructs or not.

3 - Project
   3.1 - General Questions
       3.1.1 - What has been successfully done in the past on this board?
       3.1.2 - Can my project with these specifications fit the FPGA chip?
       3.1.3 - How complex the project is expected?
       3.1.4 - What are the minimum requirements?
       3.1.5 - How to estimate the clock frequency?
       3.1.6 - How to improve the clock speed?
       3.1.7 - Don't use the Muxes from Xilinx Core Generator!
       3.1.8 - Should we write our own ALU in Verilog?
       3.1.9 - How to build a register file?
       3.1.10 - Why do we have to use "mdlring.v"?
   3.2 - Version Control
       3.2.1 - How to do version control?
       3.2.2 - Which one is the working version?
       3.2.3 - What changes did you make to my file?
       3.2.4 - One of the many possible ways to do version control?
   3.3 - Team Scheduling
       3.3.1 - How are we going to schedule the project?
       3.3.2 - What is realistic and what is not?
       3.3.3 - How are we going to make up if we want to take break during Spring break?
       3.3.4 - Are we going to work during Spring break?
       3.3.5 - What is your plan for this semester?
   3.4 - Architecture and Microarchitecture Review
       3.4.1 - Can I be late or absent because of my interview?
       3.4.2 - What is the format of the reviews?
       3.4.3 - What are we going present in Architecture review?
       3.4.4 - What are we going present in Microarch. review?
   3.5 - Progress Review
       3.5.1 - What should the TA do when some students are too busy with other activities?
       3.5.2 - When a team is not going to finish the project in time?
       3.5.3 - When a team is going to finish the project early with a fairly low design complexity compared to others’?
   3.6 - Project Demonstration
       3.6.1 - What are we expected to show in the demonstration?
       3.6.2 - How long would it take?
       3.6.3 - What should we do in the demo if we cannot get it to work in time?
       3.6.4 - Can we get an extension?
       3.6.5 - What should we put in final presentation/demonstration ?
       3.6.6 - What kinds of program are expected?
   3.7 - Project Report
       3.7.1 - What is the format?
       3.7.2 - How thorough this report is expected?
       3.7.3 - What are the audiences of this report?
       3.7.4 - What is a good annotation in the report?
       3.7.5 - How to make the code printouts?

4 - Midterm
   4.1 - What is the weight of this exam?
   4.2 - Why is it important to your grade?

5 - Software
   5.1 - Core Generator
       5.1.1 - How is each core customized to the users’ needs?
       5.1.2 - Where are the actual cores located in the NT or Win2K machine?
       5.1.3 - How does it fail to compile this particular core in ModelSim ?
       5.1.4 - Is barrel shifter available in the core library?
       5.1.5 - Why do we have to use arithmetic cores?
       5.1.6 - How to generate pipeline registers?
       5.1.7 - Avoid using MUXs from Core Gen.
       5.1.8 - What is the area complexity of this core?
       5.1.9 - Some generated cores may contain bugs and may not implement correctly.
   5.2 - Verilog Coding
       5.2.1 - Possible zero delay oscillation.
       5.2.2 - How to implement a bidirectional bus?
       5.2.3 - Some misunderstandings between input and output variables
       5.2.4 - Some misunderstandings on the "reg" variable.
       5.2.5 - Non-blocking vs. blocking assignments in the always block
       5.2.6 - I was wondering if there is any documentations on the memory model as the one on the web is written in vhdl. IS there any other way?
       5.2.7 - Good Verilog coding for synthesis references:
   5.3 - ModelSim
       5.3.1 - Why did ModelSim crash on me?
       5.3.2 - What is an SDF file?
       5.3.3 - What is the meaning of signal with "Red" color in the Waveform window?
       5.3.4 - What is the meaning of signal with "Blue" color in the Waveform window?
       5.3.5 - How to force a signal on a bidirectional bus?
       5.3.6 - How to do system simulation?
       5.3.7 - Post-synthesis simulation
       5.3.8 - Post-implementation (timing) simulation
       5.3.9 - Issues to be concerned while using a memory model ($readmemh)
       5.3.10 - What should I do if ModelSim runs out of physical memory?
       5.3.11 - How was the simprim library created?
       5.3.12 - What is simprim library?
       5.3.13 - What is unisim library?
       5.3.14 - Do you know where to find documentation for force file syntax?
   5.4 - GXSLoad 4.0
       5.4.1 - How to download the SRAM contents?
       5.4.2 - Why the SPART doesn’t work with GXSLoad 4.0?
       5.4.3 - What is the format of Intel Hex-32 file?
       5.4.4 - What is the procedure to run our processor with its program?
   5.5 - FPGA Express
       5.5.1 - What do these warnings mean?
       5.5.2 - How can we find latches in your design?
       5.5.3 - How to avoid inferring latches?
       5.5.4 - A combinational circuit?
       5.5.5 - My design takes too long to synthesize.
       5.5.6 - What is the meaning of "preserve hierarchy"?
       5.5.7 - How to estimate the design complexity?
       5.5.8 - How to estimate the delay?
       5.5.9 - How to make my design smaller?
       5.5.10 - What clock frequency should we target at?
       5.5.11 - What is a .ncf file?
       5.5.12 - HDL-394 (3 Occurrences) Warning: Unconditional concurrent assignment to tristate value in routine audio line 9 in file 'H:/Kimera/working_directories/mem_alu_cont/audio.v', may not result in hardware.
       5.5.13 - HDL-307 (1 Occurrence) Warning: Latch inferred in design 'Control_Unit' read with 'hdlin_check_no_latch'.
       5.5.14 - FPGA-pmap-18 (15 Occurrences) Warning: The port type of port '/top_module/laddr<15>' is unknown. An output pad will be inserted
       5.5.15 - FPGA-CHECK-9 (1 Occurrence) Warning: The net '/top_module/laddr<0>' is a feed through net
       5.5.16 - error #151 Synopsis Internal Error
       5.5.17 - What is a good way to write a simple finite state machine?
   5.6 - Xilinx Design Manager
       5.6.1 - What do these warnings mean?
       5.6.2 - What are basic steps to implement a design on FPGAs?
       5.6.3 - Why does it take too long to implement?
       5.6.4 - How to speedup the implementation?
       5.6.5 - Where to find answers related to FPGA synthesis and implementation?
       5.6.6 - Why did my implementation fail and say not enough pins?
       5.6.7 - Warning: Timing errors: some clock frequency fails to meet the specified clock frequency.
       5.6.8 - FATAL_ERROR:Anno:ResolverImp.c:547:1.8.16.2 - Semantic check failed for physical block "xxx" (P4138)
       5.6.9 - What is the upper complexity limit for an implementable project?

6 - Hardware
   6.1 - XSV800 Board
       6.1.1 - Is it "ON" or "OFF"?
       6.1.2 - Why can't I turn this board on?
       6.1.3 - Is the FPGA bit file being downloaded?
       6.1.4 - Which LED is connected to which FPGA pin?
       6.1.5 - Why can’t we use the internal clock?
       6.1.6 - Why do we have two sources of clock signal, external and internal?
       6.1.7 - How the SRAM banks and the expansion headers are connected?
       6.1.8 - How to probe the internal signals?
       6.1.9 - What is the function of each jumper?
       6.1.10 - How to perform hardware debugging using the logic analyzer?
       6.1.11 - Are there other colleges using this XSV board?
       6.1.12 - Where is the "Reset" button for our design located on the board?
   6.2 - VGA
       6.2.1 - How does the VGA work?
       6.2.2 - How to program a RAMDAC?
       6.2.3 - Is there any other VGA example?
       6.2.4 - The most important concern about using VGA display.
       6.2.5 - What are the differences between the resistor network DAC and the RAMDAC?
       6.2.6 - What is the minimum clock frequency to use VGA?
       6.2.7 - Why the pin "TRSTE" on Ethernet chip is set to "1"?
       6.2.8 - How many colors can a RAMDAC display?
       6.2.9 - What is the color palette?
       6.2.10 - We are working on making vga colors from 6 bits and wanted to know if there was a document that could tell us if we send a specific color to the DAC, what is color that will come out?
       6.2.11 - Also, is the VGA color that comes out of the DAC in 24 bit and is just clocked into the monitor or what is the format that it needs?
       6.2.12 - We need 256 x 240 pixels, does that mean we cannot use any clock slower than about 10.2MHz to get 256 pixels per line? We wanted to use a slower clock.
       6.2.13 - How to resize the VGA screen?
       6.2.14 - We are using the RAMDAC and the colors we get out of it are faded. You can only see the colors when the brightness is turned up all the way.
       6.2.15 - Do you have any thoughts on how we can fix this?
       6.2.16 - Is there possibly anything we overlooked?
   6.3 - Audio Codec
       6.3.1 - Any example on how to use the audio codec?
       6.3.2 - Suppose I have a 4-bit signal, continuously updated, which I want to feed to a DAC (4bit,16steps of output voltage) which drives a speaker.
       6.3.3 - I would need about 4 or 5 of these DAC's, as I have 4 or 5 4 bit signals to drive speakers.
       6.3.4 - I am a bit confused on how to actually instantiate this codec now and run my timing sim with my module, feeding the codec(and spkr), since the example is VHDL and seems to be looping to memory and the codec datasheet doesnt give Verilog implementation advice.
       6.3.5 - I tried again with the vhdl loopback example, and I can't get it to synthesize. I get the error "Library logical name CODEC is not mapped to a host directory. (VSS-1071)" Do you remember how you got the example code to synthesize correctly?
       6.3.6 - I read something about jumpers needing to be set, but I think that is for a different XESS board. Do I need to change any jumper settings for the audio codec to work correctly?
       6.3.7 - According to the documentation we need XS40 and XStend v1.2 or v1.3. Are these available to us?
       6.3.8 - Which part of the codec datasheet should I pay more attention to?
   6.4 - Block SRAM
       6.4.1 - Is the contents of the BRAMs reset to the initial state when we reset the board? I'm just curious because there is not reset pin on any of the cores, so I'm assuming that the contents will be flushed to the initial value on reset. Is this right?
       6.4.2 - How to instantiate a block of memory of this entries and bit width?
       6.4.3 - How fast is the BRAM?
       6.4.4 - ERROR:NgdBuild:432 - logical block 'myMem/myI_Cache/ram_TVD' with type 'bram_11bits' is unexpanded
   6.5 - DLL
       6.5.1 - How to use the DLLs on the FPGA?
       6.5.2 - What is the minimum input clock freq?
       6.5.3 - What do we get from the DLL?
       6.5.4 - Cascading DLLs is not recommended!
       6.5.5 - What is BUFG?
       6.5.6 - What is IBUFG?
       6.5.7 - Why can't we use DLL_Lock signal to reset the system once the DLL locks?
       6.5.8 - What are the additional frequency restrictions for the DLLs and how you found out what those limits?
   6.6 - SRAM Banks
       6.6.1 - Is it possible to use one of the two SRAM banks on the FPGA board for D-cache, and the other for I-cache? It seems like this would allow D-cache and I-cache operations to occur in parallel.
       6.6.2 - Or, is it more realistic to assume that I-cache and D-cache must both go to one main memory, comprised of both banks of SRAM?
       6.6.3 - What is the access time of on-board (external) SRAM?
   6.7 - Virtex FPGA
       6.7.1 - How do I use the registers/Flip-Flops in the IOB?