6 - Hardware

6.1 - XSV800 Board
   6.1.1 - Is it "ON" or "OFF"?
   6.1.2 - Why can't I turn this board on?
   6.1.3 - Is the FPGA bit file being downloaded?
   6.1.4 - Which LED is connected to which FPGA pin?
   6.1.5 - Why can’t we use the internal clock?
   6.1.6 - Why do we have two sources of clock signal, external and internal?
   6.1.7 - How the SRAM banks and the expansion headers are connected?
   6.1.8 - How to probe the internal signals?
   6.1.9 - What is the function of each jumper?
   6.1.10 - How to perform hardware debugging using the logic analyzer?
   6.1.11 - Are there other colleges using this XSV board?
   6.1.12 - Where is the "Reset" button for our design located on the board?

6.2 - VGA
   6.2.1 - How does the VGA work?
   6.2.2 - How to program a RAMDAC?
   6.2.3 - Is there any other VGA example?
   6.2.4 - The most important concern about using VGA display.
   6.2.5 - What are the differences between the resistor network DAC and the RAMDAC?
   6.2.6 - What is the minimum clock frequency to use VGA?
   6.2.7 - Why the pin "TRSTE" on Ethernet chip is set to "1"?
   6.2.8 - How many colors can a RAMDAC display?
   6.2.9 - What is the color palette?
   6.2.10 - We are working on making vga colors from 6 bits and wanted to know if there was a document that could tell us if we send a specific color to the DAC, what is color that will come out?
   6.2.11 - Also, is the VGA color that comes out of the DAC in 24 bit and is just clocked into the monitor or what is the format that it needs?
   6.2.12 - We need 256 x 240 pixels, does that mean we cannot use any clock slower than about 10.2MHz to get 256 pixels per line? We wanted to use a slower clock.
   6.2.13 - How to resize the VGA screen?
   6.2.14 - We are using the RAMDAC and the colors we get out of it are faded. You can only see the colors when the brightness is turned up all the way.
   6.2.15 - Do you have any thoughts on how we can fix this?
   6.2.16 - Is there possibly anything we overlooked?

6.3 - Audio Codec
   6.3.1 - Any example on how to use the audio codec?
   6.3.2 - Suppose I have a 4-bit signal, continuously updated, which I want to feed to a DAC (4bit,16steps of output voltage) which drives a speaker.
   6.3.3 - I would need about 4 or 5 of these DAC's, as I have 4 or 5 4 bit signals to drive speakers.
   6.3.4 - I am a bit confused on how to actually instantiate this codec now and run my timing sim with my module, feeding the codec(and spkr), since the example is VHDL and seems to be looping to memory and the codec datasheet doesnt give Verilog implementation advice.
   6.3.5 - I tried again with the vhdl loopback example, and I can't get it to synthesize. I get the error "Library logical name CODEC is not mapped to a host directory. (VSS-1071)" Do you remember how you got the example code to synthesize correctly?
   6.3.6 - I read something about jumpers needing to be set, but I think that is for a different XESS board. Do I need to change any jumper settings for the audio codec to work correctly?
   6.3.7 - According to the documentation we need XS40 and XStend v1.2 or v1.3. Are these available to us?
   6.3.8 - Which part of the codec datasheet should I pay more attention to?

6.4 - Block SRAM
   6.4.1 - Is the contents of the BRAMs reset to the initial state when we reset the board? I'm just curious because there is not reset pin on any of the cores, so I'm assuming that the contents will be flushed to the initial value on reset. Is this right?
   6.4.2 - How to instantiate a block of memory of this entries and bit width?
   6.4.3 - How fast is the BRAM?
   6.4.4 - ERROR:NgdBuild:432 - logical block 'myMem/myI_Cache/ram_TVD' with type 'bram_11bits' is unexpanded

6.5 - DLL
   6.5.1 - How to use the DLLs on the FPGA?
   6.5.2 - What is the minimum input clock freq?
   6.5.3 - What do we get from the DLL?
   6.5.4 - Cascading DLLs is not recommended!
   6.5.5 - What is BUFG?
   6.5.6 - What is IBUFG?
   6.5.7 - Why can't we use DLL_Lock signal to reset the system once the DLL locks?
   6.5.8 - What are the additional frequency restrictions for the DLLs and how you found out what those limits?

6.6 - SRAM Banks
   6.6.1 - Is it possible to use one of the two SRAM banks on the FPGA board for D-cache, and the other for I-cache? It seems like this would allow D-cache and I-cache operations to occur in parallel.
   6.6.2 - Or, is it more realistic to assume that I-cache and D-cache must both go to one main memory, comprised of both banks of SRAM?
   6.6.3 - What is the access time of on-board (external) SRAM?

6.7 - Virtex FPGA
   6.7.1 - How do I use the registers/Flip-Flops in the IOB?

6.1 - XSV800 Board

6.1.1 - Is it "ON" or "OFF"?
Check the LED next the ATX power supply connector.

6.1.2 - Why can't I turn this board on?
Check the explanation provided in the Lab environment handout.

6.1.3 - Is the FPGA bit file being downloaded?
Check if some of the 7-segment LEDs are blinking. If so, the bit file is being downloaded.

6.1.4 - Which LED is connected to which FPGA pin?
Check the pin list section of the XSV800 Manual.

6.1.5 - Why can’t we use the internal clock?
Internal clock frequency is cumbersome to change. You have to follow the procedure described in the XSV800 manual.

6.1.6 - Why do we have two sources of clock signal, external and internal?
The goal is to provide an alternative to the internal clock. The frequency of the external clock is easy to change in small continuum.

6.1.7 - How the SRAM banks and the expansion headers are connected?
The data and address pins of each SRAM bank are assigned to the left and right header pins respectively.

6.1.8 - How to probe the internal signals?
The only way to probe the internal signals other than the SRAM data and address buses is via either left or right header pins. In order to do so, the

6.1.9 - What is the function of each jumper?
There are certain important jumpers on the XSV800 board.

6.1.10 - How to perform hardware debugging using the logic analyzer?
The procedure consists of several steps:
1. Duplicate the signals to be probed that are not connected to either left or right header
2. declare them as output wires at the topmost level
3. assign those added output wires to the UCF file correctly
4. Hook up the corresponding pods of the logic analyzer
5. Assign the names to the right pods and save the configuration to either a floppy or the harddrive

6.1.11 - Are there other colleges using this XSV board?
There are many of them: University of Queensland, U. of Illinois ECE311, XcoNet at U. of Hawaii, and many others.

6.1.12 - Where is the "Reset" button for our design located on the board?
You can assign (map) the Reset signal to one of the push buttons, SW1 to SW4 using the UCF file.

6.2 - VGA

6.2.1 - How does the VGA work?
Simple VGA Idea and VGA RAMDAC btl481a datasheet.

6.2.2 - How to program a RAMDAC?
A VHDL example is provided at The class web page.

6.2.3 - Is there any other VGA example?
A VHDL example from University of Queensland in a Zip file.

6.2.4 - The most important concern about using VGA display.
The least significant half of the right memory bank is shared with the 8-bit output pins of VGA RAMDAC

6.2.5 - What are the differences between the resistor network DAC and the RAMDAC?
The resistor network DAC can provide at most 64 (2^6) colors. The RAMDAC can get up to 256 colors out of 16 million ones.

6.2.6 - What is the minimum clock frequency to use VGA?
The pixel (clock) rate to read each pixel depends on the screen resolution and the vertical refresh rate (mostly fixed at about 60 Hz).

6.2.7 - Why the pin "TRSTE" on Ethernet chip is set to "1"?
That's because some FPGA pins are shared by both RAMDAC chip and the Ethernet chip. The latter one must be disabled to get the right colors programmed to the RAMDAC.

6.2.8 - How many colors can a RAMDAC display?
It can simultaneously display 256 colors per palette. Each color must be specified using a 24-bit pattern, 8 bits per R, G, and B.

6.2.9 - What is the color palette?
Each palette (color table) is a simple way to store most frequently used colors.

6.2.10 - We are working on making vga colors from 6 bits and wanted to know if there was a document that could tell us if we send a specific color to the DAC, what is color that will come out?
If you combine RGB at every combination, you will get 8 colors, R,G,B,White, Magenta, Cyan, Black, and Purple. Now you have 6-bit DAC, 2 bits for each color, R,G, and B. You basically will get all the combinations of 64 colors. I cannot tell you all the names of those colors. It's going to be a very coarse shade of all colors. Some may be useful and some are not.

6.2.11 - Also, is the VGA color that comes out of the DAC in 24 bit and is just clocked into the monitor or what is the format that it needs?
The basic idea of VGA display is the scanning of an array of memory locations at constant rate through the entire screen. The electron gun will scan from left to right back and forth from the top-left to bottom-right of the screen. Each pixel corresponds to a memory location and its color corresponds to how you encode the bit pattern.

6.2.12 - We need 256 x 240 pixels, does that mean we cannot use any clock slower than about 10.2MHz to get 256 pixels per line? We wanted to use a slower clock.
The chip has 4 DLLs (delay lock loops) to divide the clock down for you. It can divide the input clock (10.2 MHz) by 1.5, 2, 3, 4,.. to the frequency you want.

6.2.13 - How to resize the VGA screen?
The screen can be resized to any resolution as long as the timing requirements of the VGA monitor are satisfied. The specifications of the HP D1193A Ultra VGA monitor is listed in the following table.

6.2.14 - We are using the RAMDAC and the colors we get out of it are faded. You can only see the colors when the brightness is turned up all the way.
You should check the jumpers to see whether you're really using the RAMDAC or the resister A2D network

6.2.15 - Do you have any thoughts on how we can fix this?
You're supposed to tristate the TRSTE pin of ethernet chip. Please doublecheck the VHDL source code.

6.2.16 - Is there possibly anything we overlooked?
The brightest white is RGB=0xFFFFFF of the RAMDAC. The brightest red is RGB=0xFF0000 and so on.

6.3 - Audio Codec

6.3.1 - Any example on how to use the audio codec?
Two VHDL examples provided by:
* Xess, Inc.: Audio Loopback in VHDL
* University of Queensland: Description and Sources

6.3.2 - Suppose I have a 4-bit signal, continuously updated, which I want to feed to a DAC (4bit,16steps of output voltage) which drives a speaker.
The audio DAC takes a 16-bit sample in serial at certain sampling frequency. You can map your 4-bit sample to a 16-bit sample to drive the audio DAC.

6.3.3 - I would need about 4 or 5 of these DAC's, as I have 4 or 5 4 bit signals to drive speakers.
You can certainly combine (sum) these output signals sample by sample (if they are output at the same frequency) and then map the result to a 16-bit sample to the on-board DAC.

6.3.4 - I am a bit confused on how to actually instantiate this codec now and run my timing sim with my module, feeding the codec(and spkr), since the example is VHDL and seems to be looping to memory and the codec datasheet doesnt give Verilog implementation advice.
The VHDL loopback example can show you how to interface with the audio codec. You CANNOT instantiate the codec in timing sim. Hardware testing is the only choice for both VGA and audio anyway. You can also VHDL-Verilog mixed synthesis and simplementation

6.3.5 - I tried again with the vhdl loopback example, and I can't get it to synthesize. I get the error "Library logical name CODEC is not mapped to a host directory. (VSS-1071)" Do you remember how you got the example code to synthesize correctly?
To synthesize this CODEC library, you must create a CODEC library in FPGA Express and add the codec.vhd to it. Then you can add other vhdl files that need the CODEC library to synthesize.

6.3.6 - I read something about jumpers needing to be set, but I think that is for a different XESS board. Do I need to change any jumper settings for the audio codec to work correctly?
As far as I can remember, I didn't set any jumper on the board. I also believe that you know the mode that this CODEC is set to by its peripheral circuit.

6.3.7 - According to the documentation we need XS40 and XStend v1.2 or v1.3. Are these available to us?
All the boards including the XSV board use the same CODEC chip. The posted audio zip file has been tested.

6.3.8 - Which part of the codec datasheet should I pay more attention to?
If you check the schematics of the XSV board, you will find that the CODEC is programmed as the following:
CMODE="L" ("0") => MCLK = 256 fs (fs = sampling freq)
MODE 2 (DIF1="1", DIF0="0") => SCLK >= 40 fs (Table 2) = 64 fs (Table 1)
Please look at the timing diagram (fig. 3) of mode 2 on page 11 of the codec datasheet.
Mode 2 is the most straightforward mode of this codec.
LRCK = LeftRight Clock

6.4 - Block SRAM

6.4.1 - Is the contents of the BRAMs reset to the initial state when we reset the board? I'm just curious because there is not reset pin on any of the cores, so I'm assuming that the contents will be flushed to the initial value on reset. Is this right?
The contents of BRAM can be reset by a reset signal. The built-in global reset signal can reset most of the components including all FFs and o/p register of the BRAM except the BRAM contents. This module is called startup_virtex which will be automatically instantiated by the Design Manager.

6.4.2 - How to instantiate a block of memory of this entries and bit width?
The only way to use Block SRAM is through the Xilinx Core Generator.

6.4.3 - How fast is the BRAM?
The Block SRAM itself is reasonably fast. However, your design with Block SRAM may be able to achieve just less than 20 MHz.

6.4.4 - ERROR:NgdBuild:432 - logical block 'myMem/myI_Cache/ram_TVD' with type 'bram_11bits' is unexpanded
"unexpanded" core error during the implementation process is due to missing .edn file in the directory.

6.5 - DLL

6.5.1 - How to use the DLLs on the FPGA?
Its application note and its source code provided by Xilinx.

6.5.2 - What is the minimum input clock freq?
Based on the experiment, the minimum freq depends on the use of the DLL. As a clock divider, the input clock must be at least 15 MHz. As a clock multiplier, it must be about 20 MHz.

6.5.3 - What do we get from the DLL?
From the app. note above, DLL provides either the divided clock or the multiplied clock depending on what it is programmed and other phases, 90, 180, 270-degree, of the target clock.

6.5.4 - Cascading DLLs is not recommended!
That's because of the minimum freq required by the DLL. High clock freq may cause the implementation tool to fail.

6.5.5 - What is BUFG?
BUFG is a global clock buffer associated with the clock distribution tree. For this Virtex FPGA, there are 4 DLLs and 4 BUFGs.

6.5.6 - What is IBUFG?
IBUFG is an input clock buffer associated with the clock pin. For this Virtex FPGA, there are 4 clock pins and 4 IBUFGs.

6.5.7 - Why can't we use DLL_Lock signal to reset the system once the DLL locks?
About DLL_Lock signal, it is not guaranteed that its lock signal will be asserted whenever the DLL is locked (even in timing simulation).

6.5.8 - What are the additional frequency restrictions for the DLLs and how you found out what those limits?
The restrictions were found from both timing simulation and hardware debugging:
For timing sim, the i/p freq >= 25 MHz.
For hw debugging, the i/p freq >= 20 MHz for clock multiplication >= 15 MHz for clock division.
These numbers may vary a bit and still apply for cascading DLLs. The DLL_LOCK may not be asserted in functional, timing sim, and even hardware debugging. Note that the input freq of 12.5 MHz is also reported.

6.6 - SRAM Banks

6.6.1 - Is it possible to use one of the two SRAM banks on the FPGA board for D-cache, and the other for I-cache? It seems like this would allow D-cache and I-cache operations to occur in parallel.
Let us treat the FPGA as a processor with on-chip cache and the SRAM banks as the main memory.

6.6.2 - Or, is it more realistic to assume that I-cache and D-cache must both go to one main memory, comprised of both banks of SRAM?
That would be the most realistic assumption.

6.6.3 - What is the access time of on-board (external) SRAM?
From its specification, the typical access time is 15 ns. With interconnect delay from FPGA to the SRAM and back, the access time may take as long as 30 ns.

6.7 - Virtex FPGA

6.7.1 - How do I use the registers/Flip-Flops in the IOB?
Solution #1 from Xilinx Answer Database
Following are the MAP options to have registers absorbed into the IOB:
map -pr o
map -pr b
The first absorbs registers for output registers, and the second absorbs registers for both input and output registers.

Solution 2:
Virtex no longer has primitives that correspond to the synchronous elements in the IOBs. There are a few ways to infer usage of these Flip-Flops if the rules for pulling them into the IOB are followed. All FFs to be pulled into the IOB must have a fanout of 1. This applies to output and 3-state enable registers. For example, if a 32-bit bidirectional bus exists, then the 3-state enable signal must be replicated in the original design so that it will have a fanout of 1. All FFs must share the same clock and reset signal, but they can have independent clock enables. One way to pull FFs into the IOB is to use the IOB= TRUE/FALSE attribute on the instantiated FFs; this gets applied to the instance name:
INST IOB = TRUE|FALSE;
The other way to pull FFs into the IOB is to use a MAP directive. If using the command line flow, use the "-pr i/o/b" option ("i" for input FFs only, "o" for output FFs only or "b" for both input and output). If using the GUIs, go to the Implementation Options on the "Optimize and MAP" window, and use the pull-down menu that is near the bottom.

Solution 3: 3-state FFs
One way to push 3-state FFs inside the IOB is to infer the FFs in the HDL codes, and use the MAP "-pr o" or "b" option.

a standard MAC core. Xilinx also provides the datasheet and evaluation version. Please visit this web page. http://www.xilinx.com/ipcenter/ and click for list of all available IP. The interfaces between this core and the Phy chip we have are quite standard and matched. So far, I still cannot find any free core except the one from opencore.org.
http://www.opencores.org/cores/ethmac/

The solution to this problem is similar to the one below. Please check it out. The main idea is to launch Core Gen from a DOS prompt in command line at your Core Gen project subdir.
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=11203