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5 - Software
5.1 - Core Generator
5.1.1 - How is each core customized to the users’ needs?
5.1.2 - Where are the actual cores located in the NT or Win2K machine?
5.1.3 - How does it fail to compile this particular core in ModelSim ?
5.1.4 - Is barrel shifter available in the core library?
5.1.5 - Why do we have to use arithmetic cores?
5.1.6 - How to generate pipeline registers?
5.1.7 - Avoid using MUXs from Core Gen.
5.1.8 - What is the area complexity of this core?
5.1.9 - Some generated cores may contain bugs and may not implement correctly.
5.2 - Verilog Coding
5.2.1 - Possible zero delay oscillation.
5.2.2 - How to implement a bidirectional bus?
5.2.3 - Some misunderstandings between input and output variables
5.2.4 - Some misunderstandings on the "reg" variable.
5.2.5 - Non-blocking vs. blocking assignments in the always block
5.2.6 - I was wondering if there is any documentations on the memory model as the one on the web is written in vhdl. IS there any other way?
5.2.7 - Good Verilog coding for synthesis references:
5.3 - ModelSim
5.3.1 - Why did ModelSim crash on me?
5.3.2 - What is an SDF file?
5.3.3 - What is the meaning of signal with "Red" color in the Waveform window?
5.3.4 - What is the meaning of signal with "Blue" color in the Waveform window?
5.3.5 - How to force a signal on a bidirectional bus?
5.3.6 - How to do system simulation?
5.3.7 - Post-synthesis simulation
5.3.8 - Post-implementation (timing) simulation
5.3.9 - Issues to be concerned while using a memory model ($readmemh)
5.3.10 - What should I do if ModelSim runs out of physical memory?
5.3.11 - How was the simprim library created?
5.3.12 - What is simprim library?
5.3.13 - What is unisim library?
5.3.14 - Do you know where to find documentation for force file syntax?
5.4 - GXSLoad 4.0
5.4.1 - How to download the SRAM contents?
5.4.2 - Why the SPART doesn’t work with GXSLoad 4.0?
5.4.3 - What is the format of Intel Hex-32 file?
5.4.4 - What is the procedure to run our processor with its program?
5.5 - FPGA Express
5.5.1 - What do these warnings mean?
5.5.2 - How can we find latches in your design?
5.5.3 - How to avoid inferring latches?
5.5.4 - A combinational circuit?
5.5.5 - My design takes too long to synthesize.
5.5.6 - What is the meaning of "preserve hierarchy"?
5.5.7 - How to estimate the design complexity?
5.5.8 - How to estimate the delay?
5.5.9 - How to make my design smaller?
5.5.10 - What clock frequency should we target at?
5.5.11 - The logic associated with the unused output signals will be optimized away (in the Optimized Chip of FPGA Express).
5.5.12 - What is a .ncf file?
5.5.13 - HDL-394 (3 Occurrences) Warning: Unconditional concurrent assignment to tristate value in routine audio line 9 in file 'H:/Kimera/working_directories/mem_alu_cont/audio.v', may not result in hardware.
5.5.14 - HDL-307 (1 Occurrence) Warning: Latch inferred in design 'Control_Unit' read with 'hdlin_check_no_latch'.
5.5.15 - FPGA-pmap-18 (15 Occurrences) Warning: The port type of port '/top_module/laddr<15>' is unknown. An output pad will be inserted
5.5.16 - FPGA-CHECK-9 (1 Occurrence) Warning: The net '/top_module/laddr<0>' is a feed through net
5.5.17 - error #151 Synopsis Internal Error
5.5.18 - What is a good way to write a simple finite state machine?
5.6 - Xilinx Design Manager
5.6.1 - What do these warnings mean?
5.6.2 - What are basic steps to implement a design on FPGAs?
5.6.3 - Why does it take too long to implement?
5.6.4 - How to speedup the implementation?
5.6.5 - Where to find answers related to FPGA synthesis and implementation?
5.6.6 - Why did my implementation fail and say not enough pins?
5.6.7 - Warning: Timing errors: some clock frequency fails to meet the specified clock frequency.
5.6.8 - FATAL_ERROR:Anno:ResolverImp.c:547:1.8.16.2 - Semantic check failed for physical block "xxx" (P4138)
5.6.9 - What is the upper complexity limit for an implementable project?
5.1 - Core Generator
5.1.1 - How is each core customized to the users’ needs?
The .veo file that has been commented some part out and renamed as .v file is the customized core. The actual (more general) core is stored locally.
5.1.2 - Where are the actual cores located in the NT or Win2K machine?
D:\xilinx\fndtn\verilog\src\XilinxCore - on 554 Lab machines
C:\ - on CAE170 machines
5.1.3 - How does it fail to compile this particular core in ModelSim ?
Check whether the "include directory" has been specified by looking at the Options.
5.1.4 - Is barrel shifter available in the core library?
No, but a simple example of barrel shifter can be found in HEL Editor. Please look at the Design Template under Language Assistant.
5.1.5 - Why do we have to use arithmetic cores?
Provided cores such as signed/unsigned adder/subtractor/multiplier are more efficient to implement on FPGAs.
5.1.6 - How to generate pipeline registers?
Long pipeline registers generated by Core Generator are packed together as a single object. Therefore, it can be very difficult to place. Individual D flip-flops can be used instead.
5.1.7 - Avoid using MUXs from Core Gen.
These multiplexors may cause an unexpanded core problem later on in the implementation phase.
5.1.8 - What is the area complexity of this core?
The complexity report of a 16-bit adder is shown below.
5.1.9 - Some generated cores may contain bugs and may not implement correctly.
For example, the netlist (.edn files) 64-point FFT core have AN overlapping conflict. This causes a number of mapping error messages which results from four FFs are mapped to the same slice. There is an overlap according to RLOCs of these two modules, mulc and pi_add. The solution is to delete the RLOC statement of one of the two overlapping modules so that Design Manager is free to map that module anywhere nearby.
5.2 - Verilog Coding
5.2.1 - Possible zero delay oscillation.
At least one loop may form in the code by either an always block or two assign statements. For the always block case, the variables in sensitivity (input) list may coincide with the assigned (output) variables. For the assign statement case, the same thing can happen as the always block case.
5.2.2 - How to implement a bidirectional bus?
Please look at the example in PDF format.
5.2.3 - Some misunderstandings between input and output variables
They both can be used as wires. Any output variable cannot be read such as if (out==1) is invalid. If an output variable is designated as a state variable, it must be additionally declared as a "reg" variable.In addition, an output of a combinational circuit described using an "always" construct, "reg" declaration is also necessary.
5.2.4 - Some misunderstandings on the "reg" variable.
As explained earlier, a "reg" variable can be either a state variable of a sequential circuit or an output of a combinational circuit described using an "always" construct. The "reg" declaration does not always imply a register.
5.2.5 - Non-blocking vs. blocking assignments in the always block
We always recommend the students use "non-blocking" assignment as the synthesis tool cannot synthesize the "block" assignment behavior.
5.2.6 - I was wondering if there is any documentations on the memory model as the one on the web is written in vhdl. IS there any other way?
Memory model using $readmemh command in Verilog. The author also provides the system integration example.
http://www.isi.edu/~jsmoon/vlsi_frame.html
5.2.7 - Good Verilog coding for synthesis references:
From Synopsys Verilog hdlref.pdf
See also the Tools and Tips page
5.3 - ModelSim
5.3.1 - Why did ModelSim crash on me?
There are many possible reasons. One of them is that your team space may be full.
5.3.2 - What is an SDF file?
SDF stands for standard delay format. SDF file supplements the timing information to "timesim.vhd" for timing simulation. Here is the standard SDF webpage at http://www.eda.org/sdf/ approved by IEEE.
5.3.3 - What is the meaning of signal with "Red" color in the Waveform window?
It is mainly due to collision or conflict on a bidirectional bus/wire.
5.3.4 - What is the meaning of signal with "Blue" color in the Waveform window?
High impedance
5.3.5 - How to force a signal on a bidirectional bus?
Use force –deposit and check the online ModelSim manual on what it means.
5.3.6 - How to do system simulation?
module top (clk, reset_b, ...);
mltring processor(.clk(clk), .reset_b(reset_b), ... );
memory left_right_bank(.address({la,ra}), .data({ld,rd}), ... );
end;
5.3.7 - Post-synthesis simulation
The idea is similar to how to do system simulation except the mltring module must come from the Verilog output generated by FPGA Express.
5.3.8 - Post-implementation (timing) simulation
Again, the idea is exactly the same as post-synthesis except the mltring module must be from the "timesim.vhd" generated by Design Manager. You must apply the timesim.SDF at the right REGION: top/processor. I believe you applied to the top module instead. That can cause these many error messages.
5.3.9 - Issues to be concerned while using a memory model ($readmemh)
The text file that contains the data must be in the "current directory" of ModelSim.
5.3.10 - What should I do if ModelSim runs out of physical memory?
Your Verilog design may be huge in terms of the number of lines, e.g., a reorder buffer. The work around is to synthesize your design and do post-synthesis simulation instead. This is beneficial because FPGA Express can help you check the hardware while synthesizing it. However, this may take a while to fix a small bug.
5.3.11 - How was the simprim library created?
vlib simprim
vmap simprim simprim
vcom -work simprim {D:\XILINX\FNDTN\vhdl\src\simprims\simprim_Vpackage.vhd}
vcom -work simprim
{D:\XILINX\FNDTN\vhdl\src\simprims\simprim_Vcomponents.vhd}
vcom -work simprim {D:\XILINX\FNDTN\vhdl\src\simprims\simprim_VITAL.vhd}
5.3.12 - What is simprim library?
It is a collection of simulation primitives for Timing Sim only. For VHDL (timesim.vhd) coding, the primitives such as DLL, bufg, and many others can be found in D:\xilinx\fndtn\vhdl\src\simprims.
5.3.13 - What is unisim library?
It is a collection of simulation primitives for Functional Sim only. For Verilog coding, the primitives such as DLL, bufg, and many others can be found in D:\xilinx\fndtn\verilog\src\unisim.
5.3.14 - Do you know where to find documentation for force file syntax?
You should be able to find it in ModelSim User's Manual and Reference Manual.
5.4 - GXSLoad 4.0
5.4.1 - How to download the SRAM contents?
It is explained in the Downaloading and Uploading Data to the RAM section of the XSV Board Manual V.1.1.
5.4.2 - Why the SPART doesn’t work with GXSLoad 4.0?
That's because GXSLoad 4.0 uses the new version of downldpar.svf. The ltring.svf is the modified version of downldpar.svf from GXSLoad 3.0.
5.4.3 - What is the format of Intel Hex-32 file?
A HEX file is actually an ASCII file. You should follow this one, "Data-File Conversion to INTEL HEX-32 Format". I found that it is easy to read and understand. The descriptions are spread around from page 16 of the XSV manual v1.1 and the Intel Hex format (simple one) and a better Intel HEX-32 manual.
5.4.4 - What is the procedure to run our processor with its program?
Here is the sequence of how to use GXSload 4.0:
1. Download the HEX file
2. Download the ltring.svf if necessary. That means if the topmost LED of the right 7-segment is off, then it is necessary to download ltring.svf
3. Download your bit file to run the program
5.5 - FPGA Express
5.5.1 - What do these warnings mean?
Pad cells.
5.5.2 - How can we find latches in your design?
You can look for latches in both the synthesized schematic and the report. In the schematic, use find or search facility to search for "". In the results repor.,
5.5.3 - How to avoid inferring latches?
Every conditional statement or construct must be fully specified. In other word, the IF clause must be followed by an ELSE clause unless storage is expected. The SWITCH construct must contain all possible CASES including its DEFAULT.
5.5.4 - A combinational circuit?
A simple combination circuit should be written using an ASSIGN statement. A complex circuit should be written using an ALWAYS construct.
5.5.5 - My design takes too long to synthesize.
Try to use bottom up approach by synthesizing the lower modules first to make sure that they are synthesizable. The bottleneck may show up in some of the lower modules, Try to fix them one by one. Use the incremental synthesis approach in the tutorial.
5.5.6 - What is the meaning of "preserve hierarchy"?
This option in FPGA Express prevents the logic optimization between modules. In other words, the logic may not be the most optimized logic. However, it allows the user to view the synthesized logic in each module explicitly.
5.5.7 - How to estimate the design complexity?
Use FPGA Express to synthesize your module. View Results on the Optimized Chip (synthesized module). Select the Modules Tab to obtain the number of Flip-Flops, the number of LUTs and many others.
5.5.8 - How to estimate the delay?
FPGA Express can roughly estimate the critical-path delay. It has little knowledge about placing and routing delays. However, its critical-path analysis is useful to help reduce the number fan-outs or loads. The larger the number of fan-outs (loads) the longer the delay is going to occur.
5.5.9 - How to make my design smaller?
* Choose to optimize for Area in FPGA Express.
* Don't preserve the hierarchy of the final design.
* Use "one-hot" encoding for state machines instead of "binary" encoding
* Note that preserving the hierarchy can help the students debug the hardware efficiently.
5.5.10 - What clock frequency should we target at?
The target frequency can be as low as 5 MHz and as high as 2x MHz.
5.5.11 - What is a .ncf file?
It's another constraint file passed from the constraint editor in FPGA Express to the Xilinx Design Manager. The content is mostly related to the clock frequency/period.
5.5.12 - HDL-394 (3 Occurrences) Warning: Unconditional concurrent assignment to tristate value in routine audio line 9 in file 'H:/Kimera/working_directories/mem_alu_cont/audio.v', may not result in hardware.
Here is the description of this warning from FPGA Express online help. You can use it for other warnings. The following example shows an unconditional concurrent assignment to tristate value in Verilog.
Module e(m);
output m;
assign m = 1'bz;
endmodule
Since the output port 'm' is always driven to tristate value, HDL Compiler will leave the port unconnected.
5.5.13 - HDL-307 (1 Occurrence) Warning: Latch inferred in design 'Control_Unit' read with 'hdlin_check_no_latch'.
This is bad. You must get rid of this latch.
5.5.14 - FPGA-pmap-18 (15 Occurrences) Warning: The port type of port '/top_module/laddr<15>' is unknown. An output pad will be inserted
This can be resolved if you declare the port appropriately.
5.5.15 - FPGA-CHECK-9 (1 Occurrence) Warning: The net '/top_module/laddr<0>' is a feed through net
There is no circuit associated with this net (wire).
5.5.16 - error #151 Synopsis Internal Error
The fact that you didn't include the Verilog version of any core can cause this error when you synthesize.
5.5.17 - What is a good way to write a simple finite state machine?
Use "one hot" encoding because the FPGA contains a large number of flip-flops. Binary encoding of states can incur more logic than that of "one hot" encoding style.
5.6 - Xilinx Design Manager
5.6.1 - What do these warnings mean?
Online help: Xilinx Answer Database (http://www.xilinx.com/support/support.htm)
5.6.2 - What are basic steps to implement a design on FPGAs?
Translate, Map, Place and Route (the most time consuming step), Timing Analysis (the second one), Bit file generation
5.6.3 - Why does it take too long to implement?
Check the target frequency. Check the complexity (CLB utilization)
5.6.4 - How to speedup the implementation?
Set the target frequency at less that or equal to 5 MHz for a complex design. Rename xx.ncf file to yy.ncf so that the frequency constraint is relaxed.
5.6.5 - Where to find answers related to FPGA synthesis and implementation?
Online help Xilinx Answer Database http://support.xilinx.com
5.6.6 - Why did my implementation fail and say not enough pins?
You should change the part number from HQ-240 to another with high enough I/O pins, e.g., BG-560.
5.6.7 - Warning: Timing errors: some clock frequency fails to meet the specified clock frequency.
This warning is not serious because DM does not fail if that clock frequency is a divided clock frequency. Divided clock is usually slower than the DLL input clock. There are two ways to fix this problem.
1. Resynthesize the design using FPGA Express. Don't check the "skip constraint entry" if you want to specifically constrain multiple clock frequencies.
2. Edit the mltring.ncf and modify the clock period, high time, low time respectively.
5.6.8 - FATAL_ERROR:Anno:ResolverImp.c:547:1.8.16.2 - Semantic check failed for physical block "xxx" (P4138)
It used to happen to a student but disappeared after the design was reimplemented again.
5.6.9 - What is the upper complexity limit for an implementable project?
Most successful projects can utilize the logic up to 80% of the logic slices.
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