TUTORIAL

Xilinx Tutorial 5.0 (doc,pdf)
Tutorial Files (zip)

Feeling Comfortable with Logic Analyzers (pdf)

Old Tutorial

FPGA Design Tutorial 4.1 (doc,pdf)
Instructions for running the tutorial on CAE workstations (Appendix D)

Tutorial Files:
    Core Files
    Mac Files
    Non-Synthesizable Verilog File

Updates to Tutorial: 09/07/03

Note: Updated to reflect changes in Modelsim 5.7e

Outstanding Issue: Appendix C: Necessity to use "dot" notation when instantiating modules for incremental synthesis. Left out of the tutorial until issue is understood.

Mixed VHDL/Verilog and FPGA Express/Design Manager Tutorial (pdf)