1 - Tutorial FAQ

1.1 - Software Tutorial
   1.1.1 - Why do we need Xilinx Core Generator?
   1.1.2 - What are the differences between functional, post-synthesis, and timing simulations?
   1.1.3 - What is "work" library?
   1.1.4 - What is "Verilog" library in ModelSim?
   1.1.5 - What is a netlist (.edn and .edf) file?
   1.1.6 - What is logic (HDL) synthesis?
   1.1.7 - What is FPGA (netlist) implementation?
   1.1.8 - What is a UCF file?

1.2 - Hardware Tutorial
   1.2.1 - What is a pod on a logic analyzer?
   1.2.2 - What is the configuration of these 4 pods?
   1.2.3 - Why is the pulse generator so important?
   1.2.4 - What is the maximum frequency of this generator?
   1.2.5 - We should pay more emphasis on hardware tutorial especially the logic analyzer!

1.1 - Software Tutorial

1.1.1 - Why do we need Xilinx Core Generator?
It can provide a number of useful cores (modules) from basic storage to arithmetic and DSP functions. The generated cores are highly optimized in both delay time and area (CLBs).

1.1.2 - What are the differences between functional, post-synthesis, and timing simulations?
The difference is how closely the simulation results (waveforms) can imitate the real circuit. Timing simulation yields the behavior closest to the real hardware but takes longer time to achieve. Functional simulation takes the shortest amount of time to achieve with the least hardware characteristics. Post-synthesis is the compromise between these two extremes but may not always work correctly.

1.1.3 - What is "work" library?
In HDL compilation, "work" is a default library (directory) created by you to hold (store) the compiled Verilog files. "work" is a local library associated with the "current" directory of ModelSim. The user must create his/her own "work" library and keep track where the "current directory" is. It is analogous to software compilation in which a library is a collection of executable object files.

1.1.4 - What is "Verilog" library in ModelSim?
"Verilog" library is a read-only global library. The compiled code can be used or accessed anywhere. The users should not compile anything to this library.

1.1.5 - What is a netlist (.edn and .edf) file?
A netlist file is a textual representation of a circuit diagram or schematic.

1.1.6 - What is logic (HDL) synthesis?
It is a process that converts a HDL description to a netlist representation.

1.1.7 - What is FPGA (netlist) implementation?
It is a process that converts a netlist to an FPGA configuration (bit file).

1.1.8 - What is a UCF file?
It is a text file written by the user to enforce (constrain) the requirements on the FPGA configuration to behave or posses certain properties such as pin assignment, maximum clock frequency, location of a DLL, etc.

1.2 - Hardware Tutorial

1.2.1 - What is a pod on a logic analyzer?
It is a set (bus) of small probes. Each probe is an input wire to the logic analyzer. Depending on the model, the analyzer consists of 4 pods (16 probes each). Hence, it is called a 64-channel analyzer.

1.2.2 - What is the configuration of these 4 pods?
Each pod is labeled with its own ID-from 1 to 4, and color-brown, red, orange, and yellow, respectively. All the 16 probes on each pod is labeled from 0 to 15 with additional CLK and GND probes. In general little endian, probe #15 and #0 represent the most significant bit and the least significant bit respectively.

1.2.3 - Why is the pulse generator so important?
It is the main source for external clock signal.

1.2.4 - What is the maximum frequency of this generator?
Its typical maximum frequency is 26 MHz.

1.2.5 - We should pay more emphasis on hardware tutorial especially the logic analyzer!
That's quite impossible. The students in this class have a variety of backgrounds. Some may be more interested in hardware than software and vice versa. Those who are more interested in hardware can learn more from hands on experiences with the guidance from this hardware tutorial and the instructor.