ECE 554 Digital Engineering Laboratory

 TUTORIAL

 

FPGA Design Tutorial 4.1 (doc,pdf)

Instructions for running the tutorial on CAE workstations (Appendix D)

Tutorial Files

Core Files (core)

Mac Files (mac)

Non-Synthesizable Verilog File (non_syn.v)

Updates to Tutorial: 09/07/03

Note: Updated to reflect changes in Modelsim 5.7e

Outstanding Issue: Appendix C: Necessity to use "dot" notation when instantiating modules for incremental synthesis. Left out of the tutorial until issue is understood.

Feeling Comfortable with Logic Analyzers (pdf)

Mixed VHDL/Verilog and FPGA Express/Design Manager Tutorial (pdf)

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