| Week |
Topics |
Extra
Reading |
| 0.5 |
Class overview |
Moore's Law |
| 1 |
Intro. to VLSI Design |
SIA Roadmap and Design &
Test (by W. Maly) |
| 1 |
Gate level simulation |
|
| 1 |
Transistor-level simulation |
|
| 0.5 |
Power
Analysis |
|
| 1 |
Interconnect
Modeling and Optimization |
|
| 1 |
Design styles, MOS
devices, Computational complexity |
Combinatorics, Complexity |
| 0.5 |
Linear
Programming |
|
| 0.5 |
Data
Structure |
|
| 2 |
Partitioning: K&L |
|
| 2 |
Partitioning: F&M,
Simulated annealing (SA) |
|
| 2 |
Floorplanning: SA, Integer
linear programming |
|
| 2 |
Placement: Linear
Assignment, Min-cut SA, Force-directed |
|
| 2 |
Routing |
|
