Spring 2001 Schedule:
Time: 9:55 -10:45m MWF
Place: 3534 Engineering Hall
Instructor: Prof.
Charlie
Chen
Department of Electrical and Computer Engineering
Office: 3421 Engineering Hall
Phone: (608)265-1145
E-Mail: chen@engr.wisc.edu
Office Hour: 3:00~4:00pm MW
Teaching Assistant:
Ting-Yuan Wang
Department of Electrical and Computer Engineering
Office: B425 Engineering Hall/3634 Engineering Hall
Phone: (608)265-3804
E-Mail: wangt@cae.wisc.edu
Office Hour: 2:00-3:00pm TR ( EH B425 )
Course Goal:
1. Establish comprehensive understanding of VLSI CAD design from physical
design, logic synthesis, to architecture synthesis.
2. Establish solid capability for CAD tools development and enhancement.
Prerequisites:
Mainly self-contained. Familiar with C or C++ programming language.
Grading Policy:
Homework: 25%
Final project: 30%
Presentation: 10%
Midterm and Quiz: 35%
Required Text:
"VLSI Physical Design Automation: Theory
& Practice"
by Sait, Sadiq M.
Publishing Date: November 15, 1999
Publisher: World Scientific Pub Co
ISBN: 9810238835
Reference Material:
"Verilog
HDL: A Guide to Digital Design and Synthesis (Bk/CD-ROM)"
by Samir Palnitkar
Publishing Date: February 12, 1996
Publisher: Prentice Hall PTR/Sun Microsystems Press
ISBN: 0134516753
