Departmentof Electrical and Computer Engineering
University of Wisconsin - Madison
ECE 734 VLSI Array Processors for Digital Signal Processing

COURSE DESCRIPTION

Spring Semester 2008-2009 (spring 2009)


Time and Place: Lec. 1, 2:25-3:15 PM, MWF,3444 Engr. Hall
Instructors: Yu Hen Hu, 3625 Engr. Hall, Tel. 262-6724 E-mail: hu AT engr dot wisc dot edu
Credits:3
Prerequisite: ECE 431 Digital Signal Processing, ECE/CS 552 Computer Architecture, or consent of instructor. General knowledge of numerical linear algebra, signal processing algorithms, and computer architecture desirable.
Goals: This course presents design methodologies of multimedia and communication algorithms over embedded micro-architecture and platforms. The emphasis is on the joint optimization of signal processing algorithm design and architectural design space exploration. Present application domain will be on standard oriented image compression algorithms such as JPEG2000, video coding algorithms, such as H.264, and wireless communication algorithms such as 802.11g, bluetooth, ZigBee, as well as WiMAX. Embedded platforms discussed will include ASIC, Sub-word parallel, SoC and multi-core.
Topics:
  • Design and Implementations of signal processing algorithms: An overview of Multimedia and Communication Standards
  • Signal processing and Communication algorithms: linear transformations, filtering
  • Signal processing algorithm representation: Data flow graph, dependence graph, signal flow graph,
  • Pipelining and parallel processing of signal processing algorihtms
  • Algorithm transformation: iteration bounds, retiming,folding, unfoling
  • Systolic array structure and design methodology, canonical mapping of algorithm to array
  • Subword parallel ISA platform implementation strategies
  • Programmable digital signal processors (PDSP): Very long instruction word (VLIW) structures
  • Multi-core implementation strategies
  • System-on-chip platform implementation strategies
  • Re-configurable computing using field programmable gate array (FPGA)
  • Signal processing arithmetic units: distributed arithmetic, CORDIC
  • Implementation of video coding standards MPEG, and JPEG: DCT and DWT architecture, motion estimation architecture, entropy coder architecture
  • Implementation of communication algorithms: digital modulation systems
Textbook: K. K. Parhi, VLSI Digital Signal Processing Systems, Design and Implementation, John Wiley & Sons, Inc, NY, NY. Notes will be available on line.
Computer Usage: Matlab may be used to demonstrate some algorithms. Students who work on class projects may need to write C programs, MMX assembly code or TMS 3206x assembly code or use computer aided design tools to program field programmable gate array (FPGA) to implement multimedia algorithms
Homework: Two to three homework assignments will be given. In addition to problems, homework may involve hand-coding of algorithms
Grading Policy: (tentative) 30% 4 homework assignments;
40% individual class project 
30% take-home final exam

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Last Modified: December 28, 2008