Departmentof Electrical and Computer Engineering
University of Wisconsin - Madison
ECE 734 VLSI Array Processors for Digital Signal Processing


Fall Semester 2018

Time and Place: Lec. 1, 9:55 - 10:45 AM, MWF,3534 Engr. Hall
Instructors: Yu Hen Hu, 3625 Engr. Hall, Tel. 262-6724 E-mail: yhhhu AT wisc dot edu
Credits:3 creidts.
This course follows the Traditional Carnegie Definition. The class meets for three 50-minute class periods each week over the fall semester and carries the expectation that students will work on course learning activities (reading, preparation of materials, etc.) for about 3 hours out of classroom for every class period.
Course Designation: Graduate level
Official Course Description: An overview of the architectures and design methodologies of VLSI array processors for digital signal processing. Emphasis is placed on the techniques of mapping algorithms onto array structures for real time signal processing. Enroll Info: ECE 431, 552, or equiv, or cons inst.
Prerequisite: Graduate or professional standing
Goals: This course presents design methodologies and implementation issues for multimedia, wireless, computer vision and machine learning algorithms over embedded micro-architecture and platforms. The emphasis is on exploiting parallelism and specification approximation to achieve desired performance under the constraint of implementation cost.
Course Learning Outcomes: On completion of the ECE 734 course, a student will be able to
- read technical (journal and conference) papers in the field of design and implementation of signal processing algorithms
- apply ideas from those technical papers to a variety of embedded system realization problems
- present the results of their reading and exploration to the class
- apply the ideas to their own research problems (if appropriate)
  • Design and Implementations of multimedia and communication standards and algorithms
  • Basic signal processing algorithm review: linear transformations, digital filtering, multi-rate
  • Algorithm representation and parallelism: dependence graph, signal flow graph, synchronous data flow
  • Non-recurrent algorithm transformation: Pipelining and vector pocessing, retiming
  • Recurrent algorithm transformation: iteration bounds, folding, unfolding, look-ahead transform
  • Sub-word parallel ISA platform implementation strategies
  • Implementation of machine learning, deep neural network algorithms
  • Implementatoon of computer vision, stereo matching, 3D reconstruction algorithms
  • Implementation of video coding standards MPEG, and JPEG: DCT and DWT architecture, motion estimation architecture, entropy coder architecture
  • Implementation of wireless communication algorithms: WIFI, 5G, OFDM, LPDC
Textbook: There will be no official textbook. here is a list of reference books. Additional lecture notes will be post on line.
Homework: 4 to 5 homework assignments will be given.
Exams and Major Graded Work: A take home final examination will be given electronically one week prior to the specified final examination time. Students are expected to complete the final examination on their own and submit the answers electronically before the specified deadline to canvas. In addition, each student is expected to propose and conduct an individual course project. In additional to submitting a final report electronically, a student needs also to submit a proposal, and to make a project presentation toward the end of the semester.
Grading Policy: (tentative) 30% homework assignments;
50% individual class project 
20% take-home final exam

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Last Modified: September 1, 2018