A Simulation of Low Power Implementation of MPEG2 Encoder

Eric Weglarz

Background

Many devices which use digital signal processors are mobile devices that are
powered by batteries.  With the use of a finite power source, power consumption
has become a major limiting factory in the size and usefulness of DSP powered
devices.  It has been shown that if a device can be run at a lowered Voltage
and frequency, it is possible to see huge power consumption savings.  Luckily
in the DSP world it is often easy to break a single workload into multiple
parallel workloads.  Power (due to thermal issues) is also becoming a limiting
factor in the design of high-performance computers.

Proposal

In order to show the promise of parallel processing, a series of simulations
will be run on a processor power simulator.  The workload will consist of
encoding mpeg2 streams using an open source mpeg2 encoder.  Comparisons will
be made between a uniprocessor and multiprocessor case.  For the multiprocessor
case, it is assumed that the image is divided into for equal size images and
sent to four independant processors to do the encoding.  Power values will
be gathered for the uniprocessor, multiprocessor at full voltage and frequency
and at reduced frequency and voltage.  The results should show that a
multiprocessor is able to complete the workload in less time and with less
total energy than the uniprocessor case.

The simulator used will be wattch.  It is a derivative of the popular
simplescalar architecture, but provides fairly accurate power estimations.
Simplescalar is a cycle accurate processor simulator which has extension to
support a proprietary architecture (PISA) and also the Compaq Alpha
architecture.  The simulations will be run using the default PISA architecture.


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[2] D. Brooks, V. Tiwari, and M. Martonosi, Wattch: A Framework for 
Architectural-Level Power Analysis and Optimization, In International Symposium 
on Computer Architecture, June 2000, pp. 83-94.

[3]  I. Hong, M. Potkonjak, and M. Srivastava, On-Line Scheduling of Hard 
Real-Time Tasks on Variable Voltage Processor, In ICCAD98, Feb. 1998, 
pp. 653-656.

[4]  Y. Lin, C. Hwang, and A. Wu, Scheduling Techniques for Variable Voltage 
Low Power Designs, In ACM Transactions on Design Automation of Electronic 
Systems, April 1997, pp. 81-97.

[5] www.simplescalar.org

[6] www.mpeg.org