ECE734, Fall 2000 Project : 1-D Discrete Cosine Transform - Review of 1-D DCT Based 8x8 Implementations and Hardware design ------------------------------------------------------------------------------------------------------------------------------- Vijay Sundar Srinivasan Background ------------------ Many image compression-decompression methods today, including the JPEG, MPEG-1, MPEG-2, H.261 and H.263 standards, are based on the Discrete Cosine Transform and its Inverse. Most of the total processing time to encode or decode video using these standards is taken up by the calculation of the DCT and/or IDCT. A 1-D DCT often forms the core of the computation of a 8x8 2-D DCT, and hence there is considerable ongoing research in 1-D DCT based 8x8 hardware/software implementations. An efficient hardware block dedicated to the calculation of the DCT/IDCT also speeds up the performance of a digital video system considerably, and a simple hardware implementation scheme for the 1-D DCT is executed and simulated in this project for illustrating the idea. Project Goal ------------------ 1. A review of Fast 1-D DCT based hardware and software 8x8 implementations available today is compiled : comparisons will be made on the basis of speed, power(for hardware), precision, gate count(for hardware). Implementations covered will be Microprocessor-based software implementations, DSP-based implementations, VLSI array implementations and HDL-synthesizable/FPGA implementations. 2. An 8-point 1-Dimensional DCT is implemented in VHDL.Though fast algorithms for computing 1-D DCT exist, the DCT formula is directly applied as a multiplication of the 8-point input by an 8-point coefficient matrix. The objective is to obtain a functionally correct implementation. The design is synthesized (tentatively) to an appropriate Altera FPGA Device and a timing simulation is done to determine speed of computation of the DCT values. Speed comparisons are made with faster 1-D DCT based 8x8 algorithms that have been implemented in hardware. Tentative data format is 8-bit 2's complement input, 8-bit 2's complement output, 12-bit internal precision. If time permits an attempt will be made to modify the design for further data precision. References --------------- (1) "Discrete Cosine Transform - Algorithms, Advantages, Applications" by K.R. Rao and P. Yip (2) Various FPGA, VLSI and software implementation descriptions available on the web; Homepages of Intel, Altera, Xilinx, Motorola, Texas Instruments