Title: Circuit resynthesis by pipelining and simultaneous retiming and clock
scheduling
Chen, Jun and Long, Changbo


The transformation techniques, such as pipelining, retiming, and unfolding,
have been applied in various design phases in the circuit design to improve
the performance. For example, The sequential circuit synthesis tool of SIS
(http://www-cad.eecs.berkeley.edu:80/Software/software.html) has employed
retiming to improve the operation speed in edge-triggered sequential circuits.


The objective of our project is to improve the resynthesis package in SIS at
gate level. Our contributions consist of:


  1). Comparing with retiming only in SIS, gain more clock cycle reduction
        in sequential circuit by simultaneous retiming and clock scheduling.


  2). By employing the pipelining technique, reduce the critical path of
        combinational parts in the sequential circuit to meet the loop bound.