Verilog Implementation of CORDIC adaptive lattice filter (CALF)

Pranay Koka (pkoka@cs.wisc.edu)

Abstract

In this project the cordic based algorithm for an adaptive lattice filter was mapped into hardware. It involved applying techniques and algorithms like systolic array mapping, pipelining and retiming to achieve the desired objective of an efficient implementation of a the filter. The basic CALF algorithm was first analysed in-terms of the computation dependence and then the areas of improvement were spotted. The algorithm was then modified so that it could be pipelined and re-timed for speed. Systolic array mapping was also performed. This project also involved implementation of the improved version of the algorithm in verilog HDL. The filter modeled here is a 16-bit 2 – cordic stage, 2-section filter with saturation arithmetic.