Team members:  Chen, Chao-Nan ; Chu, Hsi-Cheng

Title:  Pipelined Architectures for High-Speed and 
          Area-Efficient Viterbi Decoders

Convolutional codes are widely used in many communication systems due to 
their excellent error-control performance. High-speed Viterbi decoders for
convolutional codes are of great interest for high-data-rate applications.
In the project, we go through Viterbi algorithm and discuss several 
hardware architectures for implementing a Viterbi decoder. In the hardware 
implementation of a Viterbi decoder, the ACS unit is the main bottleneck 
on the decoding speed of a Viterbi decoder. By the technique of in-place 
updating path metrics and appropriate scheduling, we can introduce 
multi-level pipelining into the ACS feedback loop and hence reduce 
critical path of the ACS unit. By this way, a high-speed, area-efficient 
Viterbi decoder is achieved.