Team members:
Chen, Wei-Jen
Lin, Yen-Ting

Title:
"Implementation of Variable-Block-Size Motion Estimation Algorithm 
Using Systolic Array Architecture"

Abstract:
Block matching algorithm (BMA), which exploits temporal redundancy 
between two adjacent video frames, plays an important role in current 
video signal compression techniques and is very computational intensive. 
However, the computation of BMA is with great regularity and is suitable 
for parallel processing. Thus the pipelined systolic array we learned 
from this course is a good candidate for implementation. In this project, 
we tried to map this algorithm into systolic array architecture and 
implemented it in Verilog.

This project can be divided into three phases. In the first phase, we 
implemented a systolic array architecture proposed by Yeo and Hu for 
fixed-size full-search BMA (with block size 4*4 and search range n = 2). 
Based on this architecture, we scaled it to 8*8 and 16*16 block size BMA 
in the second phase. In the last phase, by adding some extra interconnection 
and control, we extend our implementation to the variable-block-size version 
(with block size 4*4, 8*8 and 16*16) and showed it works for both
block-splitting 
and block-merging approach.