Project Proposal
ECE-734

* Title of the project 

An optimization of the SAFER+ algorithm for custom hardware and
TMS320C6x DSP implementation. 

* Team member
o Sachin Garg
o Vikas Sharma

* Project Highlight 

Through this project, we aim to optimize the SAFER+ algorithm.  This
algorithm is an acronym for Secure and Fast Encryption Routine and was
nominated for the Advance Encryption Standard (AES) in 1998 and was
designed by Prof.  James L.  Massey of ETH Zurich. 

One of the criteria for a good Encryption algorithm is the ease of
implementation in hardware and software.  Hence, this project has been
partitioned into two separate parts - hardware and software.  In the
hardware section, we implement the algorithm on an FPGA and also design
an ASIC with layout in 0.18um standard cell library.  The purpose of
having these is to make comparisons of performance - FPGA vs custom
hardware.  Various optimizations will be made in the hardware design
during the synthesis stage.  The results of both hardware designs will
be compared for area and speed. 

For software implementation, DSPs are a highly attractive option since
they perform certain arithmetic operations at high speed; they are often
smaller and more energy efficient than a general-purpose processor.  We
will investigate the implementation of SAFER+ on the TMS320C6x DSP
architecture.  The C source code is first compiled using the standard TI
C compiler utilizing the highest level of optimizations available.  The
generated assembly code will be, then, optimized manually.  Finally
comparison will be made between machine generated and hand-coded
programs. 

* Motivation 

SAFER+, being a DSP application, has a lot of scope for various DSP
optimizations viz.  pipelining, retiming, unfolding etc.  A few
implementations are available on the Internet, most of which are C code. 
Only few of them are optimized from DSP viewpoint.  Also few comparison
are available, that detail the performance difference between
implementation of the same algorithm on different hardware. 

* Prior art 

o Nomination of SAFER+ as Candidate for the AES, Cylink Corp.

o SAFER K-64: A Byte oriented block-ciphering algorithm, James L. 
Massey, ETH Zurich

o SAFER K-64: One year later. James L. Massey, ETH Zurich

* Approach

A prototype encryptor has already been implemented in Verilog.  It has
been tested for functional correctness and was successfully synthesized
using FPGA Express tool. 

* Expected results 

We aim to achieve three distinct implementation of SAFER+ algorithm viz. 
FPGA, semi-custom ASIC and software implementation on TMS320C6x DSP
processor and then carry out a detailed comparison of merits/demerits of
different approaches and optimizations.