Team members: 	Valia, Shamik
              	Jamkar, Saket

Title: Performance Enhancement of Video Compression algorithms using SIMD
architecture

ABSTRACT:

Video Compression standards (such as the MPEG -1,2,4,7) and
Teleconferencing standards (such as the H.2XX) are vital algorithms used
in many multimedia applications, whose performance is very critical
given the high data rates that are common for video applications. 

Motion Estimation and Discrete Cosine Transform are two steps in these
Video Compression algorithms, that consume the greatest amount of CPU
resources.  Motion Estimation involves calculating the motion vectors
for image blocks, by observing the motion of each block between a
reference frame and a target frame.  Discrete Cosine Transform is a
method to change between the time and frequency domains. 

Various techniques such as Full Search, Three-step search,
Two-dimensional logarithmic search have been proposed to obtain motion
vectors.  We plan to analyze the two popular techniques of Full Search
and Three step Search on the SIMD platform provided by the Intel’s SSE2
instructions to analyze the performance gains that can be achieved with
it. 

DCT is another resource hogger that is utilized both in Video and Image
Compression algorithms.  With an aim to obtain optimal performance for
DCT on SIMD platform we will attempt to recommend additions to the SSE2
Instruction Set Architecture that would improve its performance on this
platform.  Also we plan to provide hardware support for the Instruction
we incorporate that is scalable with the SIMD architecture.