A Reconfigurable FPGA Architecture for DSP Transforms

Subramanian Rama {srama@wisc.edu}
Vishnu Vijayaraghavan {vijayaraghav@wisc.edu}

We propose a Reconfigurable Architecture for performing a variety of DSP
transforms such as DFT, Gabor Transforms, Correlation and convolution on
the same hardware using some basic building blocks and a switching
network between them.  Such architectures would be of considerable use
in low power, low area mobile applications like mobile phones, PDAs and
other handheld devices.  In such applications most of the transforms
would be needed but not all at the same time, due to limited
multi-tasking requirements.  Hence reduced area can be achieved by using
reconfigurable hardware for such applications.  We propose to prototype
the Reconfigurable DSP Transform architecture in FPGA.  The basic
building blocks we use are the adder, multiplier, Discrete Cosine
Transform (DCT) and Discrete Sine Transform (DST).  Most DSP transforms
can be represented as a linear combination of these basic building
blocks with some switching between them for reconfiguration.  In our
multiplier design we employ the complex Imaginary radix representation
(in which the bits of the real and Imaginary parts of any complex number
are interleaved within one another and represented as a single binary
number) for the numbers as both real and Imaginary parts of any complex
multiplication could be evaluated simultaneously by use of this system. 
Efficient shut down mechanisms can be employed for selective shut down
of the unused units at any given time.  Such a shut down mechanism would
enable power savings for mobile handheld devices.  The number of
pipeline registers required, basic blocks needed for the architecture
and the shutdown mechanisms are determined at the algorithm development
stage itself.  This enables prediction of area and power in advance
before hardware simulation or synthesis as opposed to most current
methods which calculate area and power only at the end of one of these
stages.