| Team Members |
Title and Abstract |
documents |
CAD
|
| Albin, Gregory |
An algorithm to perform look-ahead
transformations on finite state machine |
Presentation, Report |
| Sachdev, Devang; Zhang, Lizheng |
Hardware - Software
Partitionin |
Presentation, Report |
| Lin, Wei Yang; Chin, Tai-Lin |
On the time
scheduling problem of uniform recurrence equations |
Presentation, Report |
| Senthilvelan, Murugappan |
Tool for the
Generation and Optimization of Data Flow Graphs from
standard filter Kernals in High Level Language |
Presentation, Report |
| Hill, Eric; and Su, Lixin |
Digital Filter
Design Space Exploration Tools |
Presentation, Report |
Implementation, Architecture
|
| Chen, Chao-Nan; Chu, Hsi-Cheng |
Pipelined
Architectures for High-Speed and Area-Efficient Viterbi
Decoders |
Presentation, Report |
| Rajagopal, Harish; and Nawani, Varun |
Design of optimized
engine for Direct Sequence Spread Spectrum Transciever |
Presentation, Report |
| Gopalakrishna, Varun; Khanikar, Prakarh |
Adaptation Behaviour
of Pipelined Adaptive Digital Filters |
Presentation, Report, code |
| Kuo, Yi-Ting; Wu, Chia-Peng |
Implementation on
video object segmentation algorithm |
Presentation, Report |
| Vijayaraghavan, Vishnu; and Rama, Subramanian |
A Reconfigurable
FPGA Architecture for DSP Transforms |
Presentation, Report |
| Wang, Liang-Kai |
Implementation of
Generic Systolic Array for Genetic Algorithm |
Presentation, Report |
| Dogra, Sajal;Ritesh, Rathore |
Architectural Effects
on DSP Algorithms and Optimizations |
Presentation, Report (tar.gz file) |
| Kulkarni, Pritam; and Singh, Vidhu |
Hardware Acceleration
of the DWT based on the Fast Lifting Wavelet Transform |
Presentation, Report (zip) |
| Zhou, Xin; and Liu, Zhiyu |
A new
implementation of DWT |
Presentation,
Report |
| Zeman, Paul; and Kenney, Robert |
Serial EBCOT Encoder |
Presentation, Report and code |
| Mandal, Saikat; and Jashnani, Youesh |
Computationally
efficient algorithm for parallel implementation of zero-tree
coding |
Presentation, Report |
| Lin, Yen-Ting; and Chen, Wei-Jen |
Implementation of
Variable-Block-Size Motion Estimation Algorithm Using
Systolic Array Architecture |
Presentation, Report (zip) |
| Lodermeier, Mark |
Sum of Absolute
Differences Hardware Accelerator For Motion Estimation
Applications |
Presentation, Report(zip) |
MMX, TI DSP Implementation
|
| Chen, Hao |
Implementation of
Turbo Code in TI TMS320C8x |
Presentation, Report |
| Valia, Shamik; and Jamkar, Saket |
Performance
Enhancement of Video Compression algorithms using SIMD
architecture |
Presentation, Report |
| Xu, Jin; and Jiang, Rong |
Implementation of MPEG2
codec with MMX/SSE/SSE2 technology |
Presentation, Report, code |
| Mehta, Ami; and Muller, Gilles |
Implementation of
JPEG2000 using SSE Instruction Set |
Presentation, Report |
| Wu, Xingxing; and Zhang, Yi |
Improvement of CT Image
Reconstruction Speed Using MMX/SSE2 |
Presentation, Report and code |
| Zhang, Peng; and Zhang, Xun |
Implementation
of JPEG 2000 component algorithm DWT in TI TMS3206 |
Presentation, Report |
| Martin, Bret; and Nasim, Maimoon |
Transformation
of Beam forming Algorithm Using MMX Instructions |
Presentation, Report |
| Garg, Sachin ; Sharma, Vikas |
An optimization of
the SAFER+ algorithm for custom hardware and TMS320C6x
DSP implementation. |
Presentation, Report |