| Authors |
Title and Proposal |
Report, Presentations |
| Ahmed,Rehan |
Superscalar Architecture Design Framework for DSP operations
| Report
Presentation
|
| Chen,Chia-Hsiung |
An FPGA Implementation of the Fast Minimum-
Redundancy Prefix Coding
| Report,
Presentation
|
| Chen,Hsin Yu |
Methods of modulation and
demodulation in OFDM system:
implement and analysis for BER
performance, hardware performance,
and hardware complexity
| Report,
Presentation
|
| Gilani,Syed Zohaib Masood |
Implementation of a parallel turbo decoder for IEEE 802.16e (Wimax)
standard
| Report,
Presentation
|
| Kolluru,Krishna Bharath |
Performance study of QM coder implementation on different platforms
| Report,
Presentation
|
| Nalamalapu,Vinod Reddy |
High Speed Systolic Array Structure for Variable Block Size Motion Estimation
| Report,
Presentation
|
| Parnerkar,Shreyas Vijay |
Implementing Memory and Run-Time Efficient
Texture Classification using
NVIDIA GPU, as a co-processor
| Report,
Presentation
|
| Shen,Shan-Hsiang |
An enhanced estimation: motion and rotation estimation
| Report,
Presentation
|
| Shoaib Bin Altaf,Muhammad |
A Parallel Viterbi Decoder Implementation for High
Throughput | Report,
Presentation
|
| Shojaei,Hamid |
Implementation of Multiple Constant Multiplication Algorithms for FIR Filters
| Report,
Presentation
|
| Soman,Vikrant Sudhir |
Accelerating Spherical Harmonic Transforms on the NVIDIA GPU
| Report,
Presentation
|
| Srinath,Shreesha |
Exploring realizations of large integer multipliers using embedded blocks in modern FPGAs
| Report,
Presentation
|
| Suryanarayanan,Nikhil |
Efficient Architectures for Eigen Value Decomposition
| Report,
Presentation
|
| Zulfiqar,Mohammad Arslan |
Sphere Decoding Algorithm for Space-Time
Block Codes
| Report,
Presentation
|