REFERENCES

The full text of papers listed in this page is strictly for classroom use in ECE 734 during the semester this course is offered. Many of these are copyrighted materials and use of these materials are subject to the limitations imposed by copyright laws applicable.

MMX references

H.264 related papers

References for Course Projects Subject Selection

Books reserved at Wendt Engineering Library:

[Ban94] U. Banerjee, Loop Parallelization, Kluwer Academic Publisher, Boston, MA, 1994,
ISBN: 0792394550 (acid-free paper)
Location: Wendt Library Book Stacks
Call Number: QA76.642 B36 1994

[Kung88] S. Y. Kung, "VLSI Array Processors", Prentice Hall, Englewood Cliffs, NJ, 1988.
ISBN: 013942749X.
Location: Wendt Library Book Stacks
Call Number: TK7874 K86 1988

[Parhi99] Keshab K. Parhi, "VLSI digital signal processing systems : design and implementation", Wiley: New York, NY, c1999.
ISBN: 0471241865 (cloth : alk. paper)
Location: Wendt Library Book Stacks
Call Number: TK7874.75 P37 1999

[Madisetti95] Vijay K. Madisetti, "VLSI digital signal processors : an introduction to rapid prototyping and Design synthesis", IEEE Press and Butterworth-Heinemann, Boston:MA, c1995.
ISBN: 0750694068
Location: Wendt Library Book Stacks
Call Number: TK7895 M5 M33 1995

[Bhatta03] Shuvra Bhattacharyya, Ed Deprettere, Jrgen Teich (eds.), "Domain-specific processors: systems, architectures, modeling, and simulation", Marcel Dekker: New York, NY 2003.
ISBN: 0824747119
Available through ENGnetBASE, http://www.engnetbase.com/books/2414/dke148_fm.pdf

[Hu2002] Yu Hen Hu (Ed.), "Programmable digital signal processors: architecture, programming, and applications" Marcel Dekker, New York, NY, c2002. ISBN: 0824706471 (alk. paper)
Available through ENGnetBASE, http://www.engnetbase.com/books/2266/dk1874_fm.pdf

Selected chapters from [Hu2002]

Journal Papers 

Abstract and full text are copyright materials and hence are password protected. Check with your instructor for the current username and password.

[Bluetooth] K. Fleming et al. "Architectural Overview of Intel's Bluetooth Software Stack", Intel technology journal, vol. 4, issue 2, May 2000. available online, [full text]

[Bluetooth2] J. Kardach, "Bluetooth Architecture Overview", Intel technology journal, vol. 4, issue 2, May 2000. available online, [full text].

[Burd96] Thomas D. Burd and Robert W. Brodersen; "Processor Design for Portable Systems" Journal of VLSI Signal Processing, 1996;

[Black97]   P. J. Black, T. H.-Y. Meng, "A 1-Gb/s, four-state, sliding block Viterbi decoder," IEEE J. Solid-State Circuits, vol. 32, no. 6, June 1997, pp. 797-805.  [full text]

[Buda00]    M. budagavi, et. al, "Wireless MPEG-4 Video communication on DSP chips," IEEE Signal Processing Magazine, vol. 17, no. 1, Jan. 2000, pp. 36-53.  [full text]

[Chang92a] S. F. Chang and D. G. Messerschmitt, Designing high throughput VLC decoder Part I - Concurrent VLSI architecture, IEEE Trans. On Circuits and Systems for Video Technology, June 1992. [full text]

[Chang92b] S. F. Chang and D. G. Messerschmitt, Designing high throughput VLC decoder Part II - Parallel decoding method, IEEE Trans. On Circuits and Systems for Video Technology, June 1992. [full text]

[feig92] Feig, E.; Winograd, S. "Fast algorithms for the discrete cosine transform", IEEE Trans. Signal Processing, vol.40, no. 9 Page(s): 2174-2193, Sep. 1992 [full text], and A summary note

[Lei92] S. M. Lei, M. T. Sun, and K. H. Tzou, Design and hardware architecture of high order conditional entropy coding for images, IEEE Trans. On Circuits and Systems for Video Technology, June 1992. [full text]

[Lyons04] Lyons, R.; Bell, A., "The swiss army knife of digital networks", IEEESignal Processing Magazine, Vol. 21, Issue 3, May 2004 Page(s):90 - 100. [Full text]

[Eyre00] J. Eyre, and J. Bier, "The evolution of DSP processors," IEEE Signal Processing magazine, March 2000, vol. 17, no.2, pp. 43-51. [full text]

[Frid00]    J. Fridman, "Sub-word parallelism in digital signal processing -- applying the TigerSHARC architecture," IEEE Signal Processing Magazine, March 2000, vol. 17, no. 2, pp. 27-35. [full text]. 

[Go96]    J. Golston, "Single-chip H.324 Videoconferencing," IEEE Micro, vol. 16, no. 4, August 1996, pp. 21-33. [full text].

[Hu92]    Y. H. Hu, “CORDIC-based VLSI architecture for digital signal processing,” IEEE Signal Processing Magazine, July 1992, pp. 16-35. [full text]

[Noll97]    Noll, P., "MPEG digital audio coding, " IEEE Signal Processing Magazine, September 1997, pp. 59-81. [full text]

[Parhi89]    K. K. Parhi, “Algorithm transformation techniques for concurrent processors,” Proc. IEEE, vol. 77, no. 12, pp 1879-1895, 1989.

[Peleg96]    A. Peleg, and U. Weiser, “MMX technology extension to the Intel architecture,” IEEE Micro, August 1996, pp. 42-50. [full text]

[Pirsch95]    P. Pirsch, N. Demassieux, and W. Gehrke, “VLSI architectures for video compression – A survey,” Proc. IEEE, vol. 83, no. 2, Feb. 1995, pp.220-246. 

[Rabay98]    J. M. Rabay et al (Ed.), “VLSI Implementation Fuels the Signal Processing Revolution,” IEEE Signal Processing Magazine, Jan. 1998. [full text]

[Rofo98a]    A. Rofougaran, et. al., "A single-chip 900-Mhz spread-spectrum transceiver in 1 micron CMOS, Part I. Architecture and transmitter design," IEEE J. Solid-State Circuits, vol. 33, no. 4, April 1998, pp. 535-547.  [full text]

[Rofo98b]    A. Rofougaran, et. al., "A single-chip 900-Mhz spread-spectrum transceiver in 1 micron CMOS, Part II. Receiver design," IEEE J. Solid-State Circuits, vol. 33, no. 4, April 1998, pp. 515-534.  [full text]

[Sikora97]    T. Sikora, “MPEG digital video coding standards,” IEEE Signal Processing Magazine, September 1997, pp. 82-100.  [full text]

[Wang95]    D. J. Wang, and Y. H. Hu, “Multiprocessor implementation of real time DSP Algorithms,” IEEE Trans. on VLSI Systems, vol. 3, no. 3,  1995, pp. 393-403.  [full text]

[White89]    S. A. White, "Applications of distributed arithmetic to digital signal processing: a tutorial review,", IEEE ASSP Magazine, Vol. 6, no. 3 , July 1989, pp. 4 -19.  [full text]

[Richards04] M. A. Richards, and G. A. Shaw, "Chips, Architectures and Algorithms: Reflections on the Exponential Growth of Digital Signal Processing Capabilities", (Pre-print)

High level synthesis

[McFarland88] Michael C. McFarland, Alice C. Parker, Raul Camposano, "Tutorial on high-level synthesis", Proceedings of the 25th ACM/IEEE conference on Design automation, June 1988, pp. 330-336. pdf full text

[paulin89] P. G. Paulin, J. P. Knight, "Scheduling and binding algorithms for high-level synthesis" Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference, June, 1989, pp. 1-6. pdf full text

[bretemitz91] Mauricio Breternitz, John Paul Shen, "Architecture synthesis of high-performance application-specific processors" Proceedings 27th ACM/IEEE design automation conference, Jan. 1991, pp. 542-548. pdf full text

[shanbhag96] N. Shanbhag, "Lower bounds on power dissipation for DSP algorithms", Proceedings of the 1996 international symposium on Low power electronics and design, pp. 43-48. pdf full text

References for Multiplierless digital filter and multiplier recoding

Online Articles

  • A Systolic Array Implementation Using FPGAs by Wayne Music (2005).

    Standard Documents

    H.264/MPEG-4 AVC Standard -- a draft dated on May 23, 2003. Here is a local copy

    JPEG2000 Final Committee Draft (3/16/2000, PDF)

    Dolby AC-3, Advanced TV digital audio compression standards, and a local copy(Jan 2006, PDF, 2.5MB)

    IS-96, CDMA speech coding standard(Feb. 1996, PDF, 300K)

    H.261 Video coding standard(March 1993, Postscript, 1M)

    MPEG4 Video Verification Model v.8(1997, MS word, 6M)

    HDTV standards page. Here is a local copy (2007, PDF, 2MB)

    Last updated: March 6, 2009