Reconfigurable Computing, SoC, Generic DSP implementation

SoC implementation issues for synthesizable embedded programmable logic cores
Wu, J.C.H.; Aken'Ova, V.; Wilton, S.J.E.; Saleh, R.
Page(s): 45- 48
[Abstract]   [PDF Full-Text (345 KB)]    

A fully programmable CMOS block matrix transform imager architecture
Bandyopadhyay, A.; Haslert, P.
Page(s): 189- 192
[Abstract]   [PDF Full-Text (364 KB)]  

Embedded software in the SoC world. How HdS helps to face the HW and SW design challenge
Pospiech, F.; Olsen, S.
Page(s): 653- 658
[Abstract]   [PDF Full-Text (498 KB)]    

Reconfigurable logic in SoC systems
Greenbaum, J.
Page(s): 5- 8
[Abstract]   [PDF Full-Text (545 KB)]    

A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA and customisable I/O
Borgatti, M.; Lertora, F.; Foret, B.; Cali, L.
Page(s): 13- 16
[Abstract]   [PDF Full-Text (522 KB)]  

A low power adaptive filter using dynamic reduced 2's-complement representation
Zhan Yu; Meng-Lin Yu; Azadet, K.; Willson, A.N., Jr.
Page(s): 141- 144
[Abstract]   [PDF Full-Text (498 KB)]    

A vector DSP for imaging
Redford, J.; Bersack, B.; Moniz, M.; Huettig, F.; Fitzgerald, D.
Page(s): 159-161
[Abstract]   [PDF Full-Text (358 KB)]    

Programmable logic IP cores in SoC design: opportunities and challenges
Wilton, S.J.E.; Saleh, R.
Page(s): 63-66
[Abstract]   [PDF Full-Text (532 KB)]    

A hardware/software solution for embeddable FPGA
Lien, F.; Feng, J.; Huang, E.; Sun, C.; Liu, T.; Liao, N.; Hightower, D.
Page(s): 71-74
[Abstract]   [PDF Full-Text (380 KB)]    

Platform design approach for re-configurable network appliances
Cmar, R.; Pasko, R.; Mignolet, J.-Y.; Vanmeerbeeck, G.; Schaumont, P.; Vernalde, S.
Page(s): 79-82
[Abstract]   [PDF Full-Text (768 KB)]    

A platform-based highly parallel digital signal processor
Richter, T.; Drescher, W.; Engel, E.; Kobayashi, S.; Nikolajevic, V.; Weiss; Fettweis, G.
Page(s): 305-308
[Abstract]   [PDF Full-Text (588 KB)]    

A low-power digital filter IC via soft DSP
Hegde, R.; Shanbhag, N.R.
Page(s): 309-312
[Abstract]   [PDF Full-Text (476 KB)]   

A one chip super graphics CPU with direct unified memory controller suitable for car information and control system
Nakatsuka, Y.; Shimomura, T.; Morita, Y.; Takami, K.; Joh, M.; Narita, M.; Yamagishi, K.; Okada, Y.; Satoh, J.
Page(s): 421-423
[Abstract]   [PDF Full-Text (380 KB)]