A VLSI
architecture for automatic speech recognition on large
vocabularies
Hauenstein, A.;
Circuits and Systems, 1992., Proceedings of the 35th Midwest
Symposium on , 9-12 Aug. 1992
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[Abstract] [PDF Full-Text (344 KB)] IEEE CNF
Parallel
VLSI neural system design for time-delay speech recognition
computing
Zhang, D.D.;
Advances in Parallel and Distributed Computing, 1997. Proceedings
, 19-21 March 1997
Pages:12 - 17
[Abstract] [PDF Full-Text (572 KB)] IEEE CNF
An
efficient VLSI architecture for HMM-based speech recognition
Jer Min Jou; Yeu-Horng Shiau;
Chen-Jen Huang;
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE
International Conference on , Volume: 1 , 2-5 Sept.
2001
Pages:469 - 472 vol.1
[Abstract] [PDF Full-Text (368 KB)] IEEE CNF
Low
power VLSI architecture of Viterbi scorer for HMM-based isolated
word recognition
Bok-Gue Park; Koon-shik Cho; Jun-Dong
Cho;
Quality Electronic Design, 2002. Proceedings. International
Symposium on , 18-21 March 2002
Pages:235 - 239
[Abstract] [PDF Full-Text (498 KB)] IEEE CNF
A
programmable application-specific VLSI architecture for speech
recognition
Jia-Ching Wang; Jhing-Fa Wang;
An-Nan Suen; Yu-Sheng Weng;
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE
International Conference on , Volume: 1 , 2-5 Sept.
2001
Pages:477 - 480 vol.1
[Abstract] [PDF Full-Text (304 KB)] IEEE CNF
A
modularized processor LSI with a highly parallel structure for
continuous speech recognition
Takahashi, J.; Hamaguchi, S.;
Tansho, K.; Kimura, T.;
Solid-State Circuits, IEEE Journal of , Volume: 26 , Issue:
6 , June 1991
Pages:833 - 843
[Abstract] [PDF Full-Text (1016 KB)] IEEE JNL
Parallel
architecture for real-time speech recognition in Spanish
Alexandres, S.; Moran, J.;
Carazo, J.; Santos, A.;
Acoustics, Speech, and Signal Processing, 1990. ICASSP-90., 1990
International Conference on , 3-6 April 1990
Pages:977 - 980 vol.2
[Abstract] [PDF Full-Text (248 KB)] IEEE CNF
Integrated
circuits for a real-time large-vocabulary continuous speech
recognition system
Stolzle, A.; Narayanaswamy, S.;
Murveit, H.; Rabaey, J.M.; Brodersen, R.W.;
Solid-State Circuits, IEEE Journal of , Volume: 26 , Issue:
1 , Jan. 1991
Pages:2 - 11
[Abstract] [PDF Full-Text (972 KB)] IEEE JNL
A DSP-based
modular architecture for noise cancellation and speech
recognition
Gomez, P.; Alvarez, A.;
Martinez, R.; Perez-Castellanos, M.; Rodellar, V.; Neito, V.;
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998
IEEE International Symposium on , Volume: 5 , 31 May-3
June 1998
Pages:178 - 181 vol.5
[Abstract] [PDF Full-Text (480 KB)] IEEE CNF
A
recursively structured solution for handwriting and speech
recognition
Lin, I.-J.; Kung, S.Y.;
Multimedia Signal Processing, 1997., IEEE First Workshop on , 23-25
June 1997
Pages:587 - 592
[Abstract] [PDF Full-Text (328 KB)] IEEE CNF
A
cepstrum chip: architecture and implementation
An-Nan Suen; Jhing-Fa Wang; Yuen-Lin
Chiang;
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International
Symposium on , Volume: 2 , 28 April-3 May 1995
Pages:1428 - 1431 vol.2
[Abstract] [PDF Full-Text (304 KB)] IEEE CNF
Speech
interface ASIC of SOC architecture for embedded application
Ming Dong; Jia Liu; Runsheng
Liu;
Signal Processing, 2002 6th International Conference on , Volume:
1 , 26-30 Aug. 2002
Pages:402 - 405 vol.1
[Abstract] [PDF Full-Text (395 KB)] IEEE CNF
A VLSI
architecture for computing the optimal correspondence of string
subsequences
Ranganathan, N.; Motamarri, R.;
Computer Architecture for Machine Perception, 1997. CAMP '97.
Proceedings Fourth IEEE International Workshop on , 20-22
Oct. 1997
Pages:290 - 294
[Abstract] [PDF Full-Text (412 KB)] IEEE CNF
Systolic
codebook generation [speech recognition]
Beresford-Smith, B.; Breckling,
J.; Schroder, H.; Summons, P.;
Speech and Audio Processing, IEEE Transactions on , Volume:
1 , Issue: 2 , April 1993
Pages:144 - 149
[Abstract] [PDF Full-Text (584 KB)] IEEE JNL