Implementation
and performance of fast parallel multi-baseline stereo vision
Webb, J.A.;
Computer Architectures for Machine Perception, 1993. Proceedings
, 15-17 Dec. 1993
Pages:232 - 240
[Abstract] [PDF Full-Text (716 KB)] IEEE CNF
VLSI
implementation of an application-specific vision chip for
overtake monitoring, real time eye tracking, and automated visual
inspection
Skribanowitz, J.; Knobloch, T.;
Schreiter, J.; Konig, A.;
Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999.
MicroNeuro '99. Proceedings of the Seventh International
Conference on , 7-9 April 1999
Pages:45 - 52
[Abstract] [PDF Full-Text (4244 KB)] IEEE CNF
Implementation
image data convolutions operations in FPGA reconfigurable
structures for real-time vision systems
Wiatr, K.; Jamro, E.;
Information Technology: Coding and Computing, 2000. Proceedings.
International Conference on , 27-29 March 2000
Pages:152 - 157
[Abstract] [PDF Full-Text (52 KB)] IEEE CNF
High-speed
FPGA-implementation of multidimensional binary morphological
operations
Velten, J.; Kummert, A.;
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003
International Symposium on , Volume: 3 , 25-28 May 2003
Pages:III-706 - III-709 vol.3
[Abstract] [PDF Full-Text (304 KB)] IEEE CNF
An
integrated system architecture for binary image understanding
Deb, A.; Ling, N.;
Computer Architectures for Machine Perception, 1993. Proceedings
, 15-17 Dec. 1993
Pages:446 - 454
[Abstract] [PDF Full-Text (780 KB)] IEEE CNF
A fast
implementation of 1-D grayscale morphological filters
Demin Wang; Dong-Chen He;
Circuits and Systems II: Analog and Digital Signal Processing,
IEEE Transactions on , Volume: 41 , Issue: 9 , Sept.
1994
Pages:634 - 636
[Abstract] [PDF Full-Text (284 KB)] IEEE JNL