; Filename:     HW2prob4.s
; Author:       Eric Hoffman 
; Description:  Solution to bunch of random meaningless tasks

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Constant definitions below: ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ARRAY_LENGTH	EQU	8		;; length of array of halfwords

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Assembler Driectives below: ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

	AREA    FLASH, CODE, READONLY
	ARM

	INCLUDE ADuC7026.inc			;MMR definitions
	EXPORT  __main				 	;Export __main so linker can find definition

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Allocate any code space constants next ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
word16				DCW	2_1101001110001011
byte0				DCB	0xC3
byte_array 			DCB 1,-2,3,-4,5,-6,7,-8,9,-10
	ALIGN								;; get back on 32-bit boundary
halfword_array_addr	DCD	halfword_array	;; Have linker setup pointer to
										;; halfword array that we can load
										;; via PC relative addressing

; main program start
__main

main_loop
		;;;;;;;;; Part f below ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		LDR		R6,	[PC, #-0x0C]			;R6 will be loaded with the pointer to halfword_array 
		MOV		R5, #0						;R5 will be index pointer (R6 is base, R5 is index)
		MOV		R4,	#0x01					;R4 will be value stored
byt_mv	STRB	R4, [R6,R5]					;Write the lower byte of R4	(this goes first because ADuc7026 is little endian)
		ADD		R5, R5, #1					;increment R5 index to point to MSB of word
		MOV		R3, R4, LSR #8				;Move upper byte of data to store (R4) into R3 (not assuming it is zero)
		STRB	R3,	[R6,R5]					;Write the upper byte (this would be more efficient to do with STRH instruction)
		MOV		R4,	R4,	LSL #1				;promote R4 to next power of 2 to store
		ADDS	R5,	R5, #1					;increment our index to next word
		CMP		R5, #(2*ARRAY_LENGTH)		;are we done yet?
		BNE		byt_mv						;if not then repeat loop
		;;;;;;;;; Part g below ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	    SUB		R6,	PC, #0x48				;R6 will point to word16 (much easier if allowed to use Pseudo instructions)
		LDRB	R7,	[R6], #1				;Load LSB into R7, and inc R6 to point to next byte
		LDRSB	R8,	[R6]					;Now load upper byte and sign extend into R8 (this would be easier with LDRSH)
		MOV		R8,	R8, LSL #8				;Promote R8 to so it represents it proper weighting (it was the upper byte)
		ORR		R7, R8, R7					;Combine the 2 into R8
		;;;;;;;;; Parts h & i below ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		LDRB	R8,	[PC, #-0x5A]			; Load byte0 us unsigned
		LDRSB	R9,	[PC, #-0x5E]			; Load byte0 with sign extension
		;;;;;;;;; Part j below ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		SUB		R12, PC, #0x61				; get a pointer to first element
		MOV		R5, #0						; R5 will be index pointer
		MOV		R10, #0xFF					; R10 will store minimum unsigned byte, so init to max possible value
min_un	LDRB	R4, [R12,R5]				; load byte into R4
        CMP		R4, R10						; compare newest data to current minimum
		MOVLS	R10, R4	   					; store new min
		ADD		R5, #1
		CMP		R5, #10
		BNE		min_un
		;;;;;;;;; Part k below ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		MOV		R5, #0						; R5 will be index pointer, reusing R12 from prior part
		MOV		R10, #0x7F					; R10 will store minimum signed byte, so init to max possible value
min_si	LDRSB	R4, [R12,R5]				; load byte into R4
        CMP		R4, R10						; compare newest data to current minimum
		MOVLT	R10, R4	   					; store new min
		ADD		R5, #1
		CMP		R5, #10
		BNE		min_si

		B		main_loop

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Allocate any data in the SRAM area next ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	AREA	SRAM,	DATA,	READWRITE		; use area directive with type DATA

halfword_array	SPACE	(ARRAY_LENGTH*2)				; allocate space for ARRAY_LENTH of halfwords

	END