; Filename:     prob5WDT.s 
; Author:       ECE 353 staff 
; Description:  This exercise used the secure clear mode of the WDT.  If Port2.0 was set
;               then the WDT would not be cleared, and would underflow and cause a reset
;               If Port2.0 was set then the WDT would be cleared once it was less than
;               half the load value and the program could run indefinitely

	ARM                             ;use ARM instruction set
       INCLUDE ADuC7026.inc
       EXPORT  __main
       IMPORT  Reset_Handler
       AREA    FLASH, CODE, READONLY

__main




;checking whether the Watchdog timer has reset. If yes, branches to spin loop.
       LDR R1,=(SYSCON_MMR_BASE)
       LDR R3,[R1,#RSTSTA]		 	; Read RSTSTA register to check source of last Reset
       TST R3,#0x0002
       BNE spin_loop   				; Last reset was caused by WDT so go to spin loop
       ;STRB R3,[R2,#GP3DAT+3]


        MOV R10,#0x47				; R10 will hold our LFSR value (initial seed is 0x47)
; configuring the timer3 (watchdog timer) and GPIO2 is configured to be inputs

        MOV R3,#00					; GPCON for all inputs
        LDR R2,=(GPIO_MMR_BASE)
        STR R3,[R2,#GP2CON]		 	; setup for all GP not periph functions
        STRB R3,[R2,#GP2DAT+3]		; setup P2 pins for input
        LDR R0,=(TIMER_MMR_BASE)
        STRB R10,[R0,#T3CLRI]		; Store initial seed in LFSR
        MOV R1,#820                 ; 25 msec WDT period
        STR R1,[R0,#T3LD]		   	; Store in re-load register
        MOV R1,#0x00F0				; Turn on WDT in secure clear mode
        STR R1,[R0,#T3CON]


;main loop

indefinite_loop
        LDRB R5,[R2,#GP2DAT]	  	; read Port2
        TST  R5,#0x0001				; Check if bit0 set
        BNE  indefinite_loop		; if so don't clear WDT
        LDRH R4,[R0,#T3VAL]			; if Port2.0 not set read T3Val
        CMP  R4,#400				; and check against half way
; you have check if P2.0 has been set to zero if yes, reset the watchdog timer.

    	BGE  indefinite_loop    ; if not over half way decremented skip WDT reset
        STRB R10, [R0, #T3CLRI] ; reset watchdog timer
        MOV  R10, R10, LSL#1    ; calculate the next value of the LFSR, do left shift
        TST  R10, #0x100    	; check if bit shifted out is a 1.
        EORNE R10, R10, #0x62   ; if yes, do XOR
        ORRNE R10, R10, #1      ; if yes, feed it back to lsb
        AND R10, R10, #0xFF     ; mask off all but least 8-bits

        B indefinite_loop

spin_loop
        B spin_loop

        END