University of Wisconsin - Madison
Department of Electrical and Computer Engineering
ECE/CS 552 Introduction to Computer Architecture
- Time and Place: 11:00 - 11:50 AM, MWF, 324 Wendt Commons
- Instructors: Yu Hen Hu , 3625 Engr. Hall,
Tel.262-6724, E-mail: hu AT engr dot wisc dot edu
- Credits: 3
- Prerequisite: ECE 352, ECE 354 or consent of instructor. Students are expected to have knowledge in Logic design and Boolean algebra, Assembly language programming, Ability to use computer aided design tools.
- Students will be able to use standard performance metrics to compare performance of different digital systems
- Students will be able to design a pipelined data path for a RISC (reduced instruction set computer) instruction set and be familiar with concepts of data dependence, pipelined hazards and out of order execution.
- Students will be able to design basic data and control cache subsystems and understand basic memory organization
- Students will be able to design a pipelined RISC micro-processor system with data cache using computer aided design tool and
validate the correctness of the design using logic simulation.
- Students will have basic understanding of modern computer architecture including multicore, GPU and cluster
- Instruction formats, instruction sets and their design
- ALU design: Adders, subtracters, logic operations
- Datapath design
- Pipelining, data dependency, data hazard, control hazard, forwarding
- Control design: Hardwired control
- Cache, cache performance and cache control
- Memory systems, virtual memory, virtual machine
- Parallel computing systems, GPU, multi-thread, cluster
- Textbook: D. Patterson and J. Hennessy, Computer Organization and Design (5e) Interactive version (MIPS)
- Computer Usage: Design assignment and class project will be assigned during the semester. This will require using verilog based desgin tools.
- Project: An individual semester design project is required for each student who enrolls in this coruse. This design project will use verilog to implement a RICS instruction architecture pipelined processor with cache memory and cache control.
- Grading Policy (tentative):
- 10 % Homework assignments
- 10 % In-class exercises
- 10 % Weekly in-class quizzes
- 20 % Midterm examination
- 30 % Final Examination
- 20 % Individual course project
Last Update: April 28, 2017
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