Two-input All-nand-gate Exclusive OR
*1/22/97 
*Define EXOR Circuit
*Four NAND Implementation
*Node 101 Is Input A, node 102 Is Input B, node
*106 Is Output
X1 101 102 103 NAND
X2 101 103 104 NAND
X3 103 102 105 NAND
X4 104 105 106 NAND
*Define subcircuit NAND
.SUBCKT NAND top_in bot_in out 
*Node 1 is VDD; node 0 is GND
M1 out top_in 1 1 tp L=0.6U W=1.2U
+AD=2.88p AS=2.88p PD=7.2U PS=7.2U
M2 out bot_in 1 1 tp L=0.6u W=1.2U
+AD=2.88p AS=2.88p PD=7.2U PS=7.2U
M3 out top_in 2 0 tn L=0.6U W=1.2U
+AD=2.88p AS=2.88p PD=7.2U PS=7.2U
M4 2 bot_in 0 0 tn L=0.6U W=1.2U
+AD=2.88p AS=2.88p PD=7.2U PS=7.2U
.ENDS NAND
*Power and load and input signals
VCC 1 0 DC 3.3
C0 106 0 0.01p
.GLOBAL 1
VA 101 0 PULSE(0 3.3 0n 0.2n 0.2n 4.8n 10n)
VB 102 0 PULSE(0 3.3 2.5n 0.2n 0.2n 4.8n 10n)
*Include MOSFET Models
.LIB '/point/usr5/k/kime/spices/scn06hp.l13' NOM
**Specify analysis and display
.DC VA 0 3.3 .01 VB 0 0 0.1
.PROBE V(106)
*Delays and Power
.TRAN .01N 20N
.PROBE V(101) V(102) V(106) 
.MEASURE avg_pow AVG power FROM=10n TO=20n
.OPTIONS PROBE POST MEASOUT
.END