Department of Electrical and Computer Engineering
University of Wisconsin - Madison
Computer Engineering Seminar
(Fall 2009-2010)

        Speaker:    Professor Nam Kim
        Time:       12:00 Noon  
        Date:       September 18, 2009 
        Location:   Room 4610, Engineering Hall  

        Subject:    Optimizing Power and Throughput of Power and 
 Thermal-Constrained Multicore Processor Considering Process Variations


As usual soft drinks will be available for those who show up in
time for the seminar. 

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       Optimizing Power and Throughput of Power and Thermal-Constrained 
             Multicore Processor Considering Process Variations
   

                                        by
                                 Professor Nam Kim
                 Departments of Electrical and Computer Engineering 
                             University of Wisconsin - Madison
	         		                Madison

Abstract:

Due to process variations, manufactured devices exhibit a large spread 
of delay and leakage power consumption both within a die and across 
dies, which have been increasing with technology scaling. As a result, 
the negative impact of process variations on the maximum operating 
frequency and the total power consumption of a processor is expected to 
worsen. Meanwhile, technology scaling has allowed integration of more 
cores in a single die, substantially improving the throughput of a 
processor running highly-parallel applications.

In this talk, first, we analyze the throughput impact of applying per-
core power gating and dynamic voltage and frequency scaling to power- 
and thermal-constrained multicore processors. To optimize the 
throughput of the multicore processors running applications with 
limited parallelism, we exploit power- and thermal-headroom resulted 
from power-gated idle cores, allowing active cores to increase 
operating frequency through supply voltage scaling. Our analysis using 
a 32nm predictive technology model shows that optimizing the number of 
active cores and operating frequency within power, thermal, and supply 
voltage scaling limits improves the throughput of a 16-core processor 
by ~16%. Furthermore, we extend our throughput analysis and 
optimization to consider the impact of within-die process variations 
leading to core-to-core frequency (and leakage power) variations in a 
multicore processor. Our analysis shows that exploiting core-to-core 
frequency variations improves the throughput of a 16-core processor 
by ~75%.


Second, to optimize the total power of many-core processors, we analyze 
the impact of 1) the number of cores, 2) parallelism in applications, 
and 3) supply voltage scaling limit due to on-die memory failure at low 
supply voltage. Our analysis shows that doubling the number of cores 
with lower than nominal supply voltage offers the most cost-effective 
power reduction, resulting in up to 65% less power consumption for 
highly-parallel applications even when supply voltage scaling is 
limited to 0.7V. The reduced power, in turn, can be used to improve 
throughput at higher voltage in power-constrained many-core processors. 
Furthermore, we extend our analysis to consider within-die core-to-core 
frequency and leakage variations. When only a subset of cores in a 
many-core processor are to be chosen to achieve a demanded throughput, 
moderately fast and leaky cores always provide optimal power 
consumption. In addition, frequency-island clocking, which allows 
independent frequency for each core, leads to ~7% less power 
consumption than global clocking, and it prefers the fastest core 
(among the chosen ones) to process the totally sequential portion of 
workload.

 
Biography: 

Nam Sung Kim is an Assistant Professor at the University of 
Wisconsin–Madison. He was with Intel as a senior research 
scientist from 2004 to 2008 after he received his Ph.D. 
degree in Computer Science and Engineering from the 
University of Michigan–Ann Arbor in 2004. He has published more 
than 30 technical papers in refereed international conferences and j
ournals and served in technical program committees of several prominent 
international conferences. He was a recipient of the award at the 
IEEE Design Automation Conference (DAC) Student Design Contest in 2001 
and the best paper award at the IEEE International Conference on 
Microarchitecture (MICRO) in 2003. He was also a recipient of Intel 
Fellowship. His research interest is robust and low-power circuits,
microarchitecture, and system design in nanoscale technology.