Department of Electrical and Computer Engineering
University of Wisconsin - Madison
Computer Engineering Seminar
(Fall 2008-2009)
Speaker: Natalie D. Enright Jerger
Time: 12:00 pm
Date: October 3, 2008
Location: Room 4610, Engineering Hall
Subject: Virtual Tree Coherence: Leveraging Regions and In-Network Multicast
Trees for Scalable Cache Coherence
As usual soft drinks will be available for those who show up in
time for the seminar.
*************************************************************************
Virtual Tree Coherence: Leveraging Regions and In-Network Multicast Trees for Scalable Cache Coherence
by
Natalie D. Enright Jerger
Department of Electrical and Computer Engineering
University of Wisconsin – Madison
Madison, Wisconsin 53706 - 1691
Abstract:
Scalable cache coherence solutions are imperative to drive the many-core
revolution forward. To fully realize the massive computation power of
these many-core architectures, the communication substrate must be
carefully examined and streamlined. There is tension between the need for
an ordered interconnect to simplify coherence and the need for an
unordered interconnect to provide scalable communication. In this work, we
propose a coherence protocol, Virtual Tree Coherence (VTC), that relies on
a virtually ordered interconnect. Our virtual ordering can be overlaid on
any unordered interconnect to provide scalable, high-bandwidth
communication. Specifically, VTC keeps track of sharers of a
coarse-grained region, and multicasts requests to them through a virtual
tree, employing properties of the virtual tree to enforce ordering amongst
coherence requests. We compare VTC against a commonly used directory-based
protocol and a greedy-order protocol extended onto an unordered
interconnect. VTC outperforms both of these by averages of 25% and 11% in
execution time respectively across a suite of scientific and commercial
applications on 16 cores. For a 64-core system running server
consolidation workloads, VTC outperforms directory and greedy protocols
with average runtime improvements of 31% and 12%.
Biography:
Natalie Enright Jerger is a PhD candidate at the University of
Wisconsin Madison. Upon finishing her PhD this December, she will be
joining the faculty at the University of Toronto as an Assistant
Professor in Computer Engineering. Her research interests
include communication architectures, cache coherence protocols and virtual
machines for many-core architectures. Natalie's dissertation research is
co-advised by Mikko Lipasti of the University of Wisconsin and Li-Shiuan
Peh of Princeton University. Her graduate work has been supported by an
IBM PhD Fellowship and a Schneider Distinguished Graduate Fellowship.
Prior to attending UW, she received her B.S. in Computer Engineering from
Purdue University.