Department of Electrical and Computer Engineering
University of Wisconsin - Madison
Computer Engineering Seminar
(Fall 2009-2010)

        Speaker:    Professor Paul Ampadu
        Time:       12:00 Noon  
        Date:       October 2, 2009 
        Location:   Room 4610, Engineering Hall  

        Subject:    Multi-Layer Cooperative Error Control for Reliable 
	                Energy-Efficient Networks-on-Chip


As usual soft drinks will be available for those who show up in
time for the seminar. 

*************************************************************************

   Multi-Layer Cooperative Error Control for Reliable Energy-Efficient Networks-on-Chip
   

                                        by
                               Professor Paul Ampadu
                 Departments of Electrical and Computer Engineering 
                             University of Rochester
	         		      New York 

Abstract:

As billions of nanoscale devices are integrated on a single chip, interconnect emerges as 
the critical bottleneck in meeting reliability and energy constraints. While the network-on-chip 
framework alleviates some challenges with many-core processing and communication, 
the reduced supply and threshold voltages that accompany aggressive technology scaling 
exacerbate system susceptibility to noise (e.g. crosstalk, soft errors, process and 
environmental variations). Thus, methods to improve interconnect reliability at 
moderate energy costs become imperative. Research in reliable interconnect design typically 
investigates solutions at a single layer (e.g. physical). This talk will present some 
cooperative techniques at the physical, datalink, and network layers in networks-on-chip 
to address transient, intermittent and permanent link errors.

Biography: 

Prof. Paul Ampadu received the PhD degree in electrical and computer engineering 
from Cornell University, NY in 2004. From 2001 to 2002 and in the summers of 1999 and 2000, 
he conducted research at the IBM T. J. Watson Research Center in Yorktown Heights, NY, 
where he investigated design and implementation of energy-efficient VLSI signal 
processing functions. From 1994 to 1995 while at Microsoft Corporation, he helped 
ship the first Japanese version of MS Word for the Macintosh and the first 32-bit 
version of Word Far East; in addition, he was a co-technical editor for 
three Microsoft Press books. His research interests are in energy-efficient 
fault-tolerant circuits and architectures for emerging nanoelectronics, 
low-voltage VLSI, and efficient design of embedded communication and 
signal processing functions. Dr. Ampadu is the author or co-author of dozens 
of scholarly articles in journals and conference proceedings. He serves 
on the IEEE Circuits and Systems technical committees on VLSI, Nano-Giga, 
and Circuits and Systems for Communication, is an associate editor for the 
Journal of Circuits, Systems, and Computers (JCSC), is a reviewer for many 
IEEE and ACM journals, and has organized and chaired several sessions at 
international conferences. Currently he is an assistant professor of 
electrical and computer engineering and directs the Embedded Integrated 
Systems-on-chip (EdISon) research group at the University of Rochester in New York. 
Dr. Ampadu has been a recipient of a Semiconductor Research Corporation (SRC) 
master's scholarship (1997-1999), an IBM doctoral fellowship (1999-2003), 
a provost fellowship (2003-2004), many federal and industry research 
grants (2004-2009), and was selected for a NASA Summer Faculty Fellowship (2005). 
Paul enjoys languages, cycling, and ping-pong in his spare time.