Department of Electrical and Computer Engineering
University of Wisconsin - Madison
Computer Engineering Seminar
(Fall 2009-2010)

        Speaker:    Professor Mike Schulte
        Time:       12:00 Noon  
        Date:       September 11, 2009 
        Location:   Room 4610, Engineering Hall  

        Subject:    FPGA-based Designs for the Large Hadron Collider at CERN


As usual soft drinks will be available for those who show up in
time for the seminar. 

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       FPGA-based Designs for the Large Hadron Collider at CERN
   

                                        by
                               Professor Mike Schulte
                 Departments of Electrical and Computer Engineering 
                             University of Wisconsin - Madison
	         		                Madison

Abstract:

When fully operational, the Large Hadron Collider (LHC) at CERN
will be the world's largest and most powerful particle accelerator,
capable of accelerating protons to over 99.999999% the speed of 
light and generating particle collisions with energies greater 
than 10 Tera-electron-Volts. Results from these collisions 
will be analyzed in an attempt to answer several important 
questions including: (1) What are the fundamental particles 
and forces that make up our Universe? (2) How do objects obtain
mass? (3) Are there extra dimensions? (4) Are there flaws in our 
current understanding of the Universe? 

Due to the tremendous amount of data generated by particle 
collisions at the LHC and the high rate at which this data 
is generated, very complex trigger systems are used to select 
potentially interesting particle collision data to process 
and archive for further study. For example, the Level-1 (L1)
Trigger System for the Compact Muon Solenoid (CMS) Experiment 
analyzes data at a rate of roughly 3 terabits/second and reduces 
it to 100 megabits/second of event data that subsequent 
systems can handle. Because of the vast amount of input data 
and the rate at which it is generated, the CMS L1 Trigger
utilizes thousands of FPGAs and ASICs, and is subject to stringent
performance requirements. These performance requirements will become 
even more severe as the LHC is upgraded over the next ten years, 
requiring a careful redesign of the CMS L1 Trigger hardware. 

In this talk, I will give an overview of the LHC, the CMS Experiment,
and some of the exciting physics phenomena they are designed help
discover. I also will present some of the FPGA-based hardware 
designs that our team is developing and analyzing for the 
CMS L1 Trigger System, and discuss some of the key challenges 
in developing flexible, high-performance hardware designs for t
his type of system.

Biography: 

Mike Schulte is an Associate Professor in Computer Engineering at
the University of Wisconsin-Madison, where he directs the Madison
Embedded Systems and Architectures Lab. His research and 
teaching interests include embedded systems, domain-specific 
processors, computer architecture, computer arithmetic, 
and digital system design.