Department of Electrical and Computer Engineering
University of Wisconsin - Madison
Computer Engineering Seminar
(Fall 2009-2010)

        Speaker:    Professor Xioqing Wen
        Time:       12:00 Noon  
        Date:       March 27, 2009   
        Location:   Room 4610, Engineering 
        Subject:    Low-Power Test Generation for Reducing 
                   Yield Loss Risk in At-Speed Scan Testing
 


As usual soft drinks will be available for those who show up in
time for the seminar. 

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           Low-Power Test Generation for Reducing Yield Loss 
                     Risk in At-Speed Scan Testing
 
             
                                   by
                          Professor Xiaoqing Wen
                      Kyushu Institute of Technology
                           Iizuka, Fukuoka, Japan


Abstract:


Power dissipation in an integrated circuit is a critical issue, not 
only in functional mode but also in test mode. Due to the non-
functional nature of test data, test clocking, and test scheduling, 
test power can be several times higher than functional power. Excessive 
test power not only causes over-heating that results in package/chip 
damage and reliability degradation but also severe power supply noise 
that leads to test-induced yield loss, especially in at-speed scan 
testing. The deep submicron (DSM) era is seeing the worsening of the 
problem of test power, to which low-power devices are specially 
vulnerable. 

This talk begins with a general review of test-power-related problems 
and basic approaches to reducing test power. Next, it describes a 
proposed scheme of using design for testability (DFT) techniques for 
reducing test power in shift mode. Following which our approach
continues with low-capture-power (LCP) test 
generation for reducing test power in capture mode so as to have
minimum circuit and performance overhead for at-speed scan testing. 
The presentation of LCP test generation includes 
basic concepts, typical techniques, and experimental results. 
Finally, this talk concludes with discussions of some future research 
topics.      

Biography: 

Xiaoqing Wen received the B.E. degree from Tsinghua University, 
Beijing, China in 1986, the M.E. degree from Hiroshima University, 
Hiroshima, Japan in 1990, and the Ph.D. degree from Osaka University, 
Osaka, Japan in 1993. From 1993 to 1997, he was a Lecturer at Akita 
University. He was a Visiting Researcher at University of Wisconsin - 
Madison from October 1995 to March 1996. He joined SynTest 
Technologies, Inc., Sunnyvale, CA, in 1998 and served as its chief 
technology officer (CTO) until 2003. In 2004, he joined the Kyushu 
Institute of Technology, Iizuka, Japan, where he is currently a 
Professor and Chair of the Department of Creative Informatics. His 
research interests include design, test, and diagnosis of integrated 
circuits. Dr. Wen holds 15 U.S. Patents, 2 Japan Patents, and 22 
pending U.S. and Japan Patents in logic built-in self-test (BIST), test 
compression, and low-capture-power (LCP) test generation. He co-
authored and co-edited two books, one on DFT and one on low-power 
testing. He received the 2008 IEICE-ISS Best Paper Award for LCP X-
filling / test generation. He is a senior member of the IEEE, a member 
of the IEICE, and a member of the REAJ.