Department of Electrical and Computer Engineering
University of Wisconsin - Madison
Computer Engineering Seminar
(Fall 2009-2010)

        Speaker:    Chunhua Yao
        Time:       12:00 pm 
        Date:       October 16, 2009    
        Location:   Room 4610, Engineering Hall 
        Subject:     Power and Thermal Constrained Test Scheduling under Deep Submicron Technologies                        

As usual soft drinks will be available for those who show up in
time for the seminar. 

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          Power and Thermal Constrained Test Scheduling under Deep 
                            Submicron Technologies

                                      by

                                  Chunhua Yao  
               Department of Electrical and Computer Engineering
                       University of Wisconsin – Madison
                         Madison, Wisconsin 53706 - 1691

Abstract:

In this deep submicron era, thermal issues are important in Integrated 
Circuit (IC) testing due to both increasing power densities and higher 
reliability requirements. Running many tests simultaneously in a 
System-on-Chip (SoC) or multi-core system can result in overheating of 
the IC, which in turn introduces reliability problems and/or damages 
the IC. Conventional power constrained test scheduling methods do not 
guarantee a thermal-safe solution. In this talk, we first propose a 
test scheduling algorithm that satisfies the resource, power and 
thermal constraints. In our algorithm, tests do not have to start at 
the completion of another test. In contrast to existing schemes, the 
proposed algorithm may also introduce cooling periods to reduce the 
overall test length of a valid schedule. To reduce the execution time 
of thermal simulation, the proposed algorithm exploits superposition 
principle to compute the thermal profile rapidly and accurately. 
Second, we propose a test partition based method to further improve the 
performance of the test scheduling. In the partition based test 
scheduling algorithm, we use a cycle-accurate power model which also 
considers the leakage power and wake-up power consumption during 
testing. We apply our test scheduling algorithm to ITC’02 SoC 
benchmarks and the results show improvements in the total test time. 

Biography: 

Chunhua Yao is a Ph.D candidate in Electrical and Computer Engineering 
at the University of Wisconsin-Madison, where he received his M.S. 
degree in Electrical Engineering in 2008.  He also received his B.S. 
degree in Electrical Engineering from Minzu University of China in 
2000. His research interests include VLSI design and testing, Built-in 
self-test, Design for testability etc.