Zhiyu Liu's HomePage



I'm Ph.D student of Electrical and Computer Engineering Department in University of Wisconsin-Madison.

My research is focusing on low power VLSI hardware design.

My advisor is Prof. Volkan Kursun. 

mailbox.gif> <font color=509 Eagle Heights, Apt L, Madison, WI 53705

phone.gif (1141 bytes)> <font color=Office: (608)890-0861

mail.gif (14893 bytes)> <font color=Email to: zhiyuliu@wisc.edu

 

Patents

  1. V. Kursun and Z. Liu, “Domino Logic Circuit Techniques for Suppressing Subthreshold and Gate Oxide Leakage,” United States Patent Pending.  
  2. V. Kursun and Z. Liu, “Low Swing Domino Logic Circuits with Multiple Supply and Ground Voltages,” United States Patent Pending.

 

Journal Publications

  1. Z. Liu and V. Kursun, “New Data Preserving MTCMOS Flip-Flops with Simple Control Circuitry,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems (in review).
  2. Z. Liu and V. Kursun, “Low Leakage Single Sleep Switch Domino Logic,” IEEE Transactions on Circuits and Systems I (in review).
  3. Z. Liu and V. Kursun, “PMOS-only Sleep Switch Dual Threshold Voltage Domino Logic in Sub-65nm CMOS Technologies,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems (in press).   
  4. Z. Liu and V. Kursun, “Leakage Biased PMOS Sleep Switch Dynamic Circuits,” IEEE Transactions on Circuits and Systems II, Vol. 53, No. 10, pp. 1093-1097, October 2006.
  5. Z. Liu and V. Kursun, “Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS technologies,” IEEE Transactions on Circuits and Systems II, Vol. 53, No. 8, pp. 692-696, August 2006.
  6. Z. Liu and V. Kursun, “Sleep Switch Dual Threshold Voltage Domino Logic with Reduced Subthreshold and Gate Oxide Leakage Current,” Microelectronics Journal, Volume 37, Issue 8, pp. 812-820, August 2006.

Conference Publications

  1. Z. Liu, S. A. Tawfik, and V. Kursun, “An Independent-Gate FinFET SRAM Cell with High Data Stability and Low Leakage Power,” the IEEE/ACM International System-on-Chip Conference, 2007 (in review).
  2. Z. Liu and V. Kursun, “New MTCMOS Flip-Flops with Simple Control Circuitry and Low Leakage Data Retention Capability,” the IEEE International Conference on Electronics, Circuits, and Systems, 2007 (in review).
  3. Z. Liu, and V. Kursun, “Low Energy MTCMOS with Sleep Transistor Charge Recycling,” Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, August 2007 (in press).
  4. R. Kumar, Z. Liu, and V. Kursun, “Fundamental Concepts of Power and Energy Measurement with Computer-Aided Design Tools,” Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, August 2007 (in press).
  5. Z. Liu and V. Kursun, “High Read Stability and Low Leakage Cache Memory Cell,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2774-2777, May 2007.
  6. V. Kursun, S.A. Tawfik, and Z. Liu, “Leakage-Aware Design of Nanometer SoC,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3231-3234, May 2007 (invited paper).
  7. Z. Liu and V. Kursun, “Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1389-1392, May 2007.
  8. Z. Liu and V. Kursun, “Charge Recycling between Virtual Power and Ground Lines for Low Energy MTCMOS,” Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, pp. 239-244, March 2007.
  9. Z. Liu and V. Kursun, “High Read Stability and Low Leakage SRAM Cell Based on Data/Bitline Decoupling,” Proceedings of the IEEE International Systems on Chip (SOC) Conference, pp. 115-116, September 2006.
  10. V. Kursun and Z. Liu, “Wide Temperature Spectrum Low Leakage Dynamic Circuit Technique for Sub-65nm CMOS Technologies,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3854-3857, July 2006.
  11. Z. Liu and V. Kursun, “Leakage Current Starved Domino Logic,” Proceedings of the ACM International Great Lake Symposium on VLSI, pp. 428-433, April 2006.
  12. Z. Liu and V. Kursun, “Leakage Biased Sleep Switch Domino Logic,” Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, pp. 318-323, March 2006.
  13. Z. Liu and V. Kursun, “Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages,” Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, pp. 31-36, March 2006.
  14. Z. Liu and V. Kursun, “High Speed Low Swing Dynamic Circuits with Multiple Supply and Threshold Voltages,” Proceedings of the IEEE International Symposium on VLSI, pp. 59-64, March 2006.
  15. Z. Liu and V. Kursun, “Shifted Leakage Power Characteristics of Dynamic Circuits Due to Gate Oxide Tunneling,” Proceedings of the IEEE International Systems on Chip (SOC) Conference, pp. 151-154, September 2005.
  16. Z. Liu and V. Kursun, “Temperature Dependent Leakage Power Characteristics of Dynamic Circuits in Sub-65nm CMOS Technologies,” Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, pp. 551-554, August 2005.
  17. Z. Liu and V. Kursun, “Bidirectional Dynamic Node Low Voltage Swing Domino Logic,” Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, pp. 295-298, August 2005.